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MC9S08DZ32F1C32 Datasheet(PDF) 6 Page - Freescale Semiconductor, Inc |
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MC9S08DZ32F1C32 Datasheet(HTML) 6 Page - Freescale Semiconductor, Inc |
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6 / 416 page  MC9S08DZ60 Series Data Sheet, Rev. 4 6 Freescale Semiconductor Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. © Freescale Semiconductor, Inc., 2007-2008. All rights reserved. This product incorporates SuperFlash® Technology licensed from SST. Revision Number Revision Date Description of Changes 1 6/2006 Advance Information for alpha samples customers 2 9/2007 Product Launch. Removed the 64-pin QFN package. Changed from standard to extended mode for MSCAN registers in register summary. Corrected Block diagrams for SCI. Updated the latest Temp Sensor information. Made FTSTMOD reserved. Updated device to use the ADC 12-bit module. Revised the MCG module. Updated the CPU Instruction Set table. Updated the TPM block module to version 3. Added the TPM block module version 2 as an appendix for devices using 3M05C (or earlier) mask sets. Heavily revised the Electricals appendix. 3 10/2007 Removed two tables that were inadvertently included in the MC9S08DZ60 version of the book. 4 6/2008 Sustaining update. Incorporated PS Issues # 2765, 3177, 3236, 3292, 3311, 3312, 3326, 3335, 3345, 3382, 2795, 3382 and 3386 PLL Jitter Spec update. Also, added internal reference clock trim adjustment statement to Features page. Updated the TPM module to the latest version. Adjusted values in Table A-13 Control Timing row 2 and in Table A-6 DC Characteristics row 24 so that it references 5.0 V instead of 3.0 V. |
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