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M95256MN3TP Datasheet(PDF) 6 Page - STMicroelectronics |
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M95256MN3TP Datasheet(HTML) 6 Page - STMicroelectronics |
6 / 44 page Description M95256, M95256-W, M95256-R 6/44 1 Description The M95256, M95256-W and M95256-R are electrically erasable programmable memory (EEPROM) devices. They are accessed by a high speed SPI-compatible bus. Their memory array is organized as 32768 x 8 bits. The device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 1 and Figure 1. The device is selected when Chip Select (S) is taken low. Communications with the device can be interrupted using Hold (HOLD). Figure 1. Logic diagram Figure 2. SO and TSSOP connections 1. See Section 10: Package mechanical data for package dimensions, and how to identify pin-1. AI12361 S VCC M95256 HOLD VSS W Q C D D VSS C HOLD Q SVCC W AI12362 M95256 1 2 3 4 8 7 6 5 |
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