MOSEL VITELIC

V827316K04S

9

V827316K04S Rev. 1.6 March 2002

AC Characteristics (cont.)

Notes: 1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.

2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, CS, RAS, CAS, WE.

3. For command/address input slew rate >=1.0V/ns

4. For command/address input slew rate >=0.5V/ns and <1.0V/ns

5. CK, CK slew rates are >=1.0V/ns

6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed

by design or tester correlation.

7. Data latched at both rising and falling edges of Data Strobes(DQS) : DQ, DM

8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete

Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.

DQS-Out edge to Data-Out edge Skew

-

0.5

-

0.5

-

0.6

ns

Data-Out hold time from DQS

-0.75ns

-

-0.75ns

-

-0.75ns

-

ns

1

Clock Half Period

min

-

min

-

min

-

ns

1

Input Setup Time (fast slew rate)

0.9

-

0.9

-

1.1

-

ns

2,3,5,6

Input Hold Time (fast slew rate)

0.9

-

0.9

-

1.1

-

ns

2,3,5,6

Input Setup Time (slow slew rate)

1.0

-

1.0

-

1.1

-

ns

2,4,5,6

Input Hold Time (slow slew rate)

1.0

-

1.0

-

1.1

-

ns

2,4,5,6

Input Pulse Width

2.2

-

2.2

-

-

-

ns

6

Write DQS High Level Width

0.4

0.6

0.4

0.6

0.4

0.6

CLK

Write DQS Low Level Width

0.4

0.6

0.4

0.6

0.4

0.6

CLK

CLK to First Rising edge of DQS-In

0.75

1.25

0.75

1.25

0.75

1.25

CLK

Data-In Setup Time to DQS-In (DQ & DM)

0.5

-

0.5

-

0.6

-

ns

7

Data-in Hold Time to DQS-In (DQ & DM)

0.5

-

0.5

-

0.6

-

ns

7

DQ & DM Input Pulse Width

1.75

-

1.75

-

2

-

ns

Read DQS Preamble Time

0.9

1.1

0.9

1.1

0.9

1.1

CLK

Read DQS Postamble Time

0.4

0.6

0.4

0.6

0.4

0.6

CLK

Write DQS Preamble Setup Time

0

-

0

-

0

-

CLK

Write DQS Preamble Hold Time

0.25

-

0.25

-

0.25

-

CLK

Write DQS Postamble Time

0.4

0.6

0.4

0.6

0.4

0.6

CLK

Mode Register Set Delay

2

-

2

-

2

-

CLK

Power Down Exit Time

10

-

10

-

10

-

ns

Exit Self Refresh to Non-Read Command

75

-

75

-

80

-

ns

Exit Self Refresh to Read Command

200

-

200

-

200

-

CLK

8

Average Periodic Refresh Interval

-

15.6

-

15.6

-

15.6

us

Parameter

Symbol

(PC1600)

(PC2100B)

(PC2100A)

Unit

Note

Min

Max

Min

Max

Min

Max