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FMS6501MSA28 Datasheet(PDF) 8 Page - Fairchild Semiconductor |
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FMS6501MSA28 Datasheet(HTML) 8 Page - Fairchild Semiconductor |
8 / 14 page © 2004 Fairchild Semiconductor Corporation www.fairchildsemi.com FMS6501 Rev. 1.0.4 8 I2C Interface Figure 4. Bit Transfer Figure 5. Definition of START and STOP conditions Operation The I2C-compatible interface conforms to the I2C spec- ification for Standard Mode. Individual addresses may be written. There is no read capability. The interface consists of two lines. These is a serial data line (SDA) and a serial clock line (SCL), both of which must be connected to a positive supply through an external resistor. Data transfer may be initiated only when the bus is not busy. Bit Transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse. Changes in the line during this time are interpreted as a control signal. Data line stable; data valid SCL SDA Change of data allowed Start and Stop Conditions The data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH, is defined as START condition (S). A LOW-to-HIGH transition of the data line, while the clock is HIGH, is defined as STOP condition (P). SP START condition STOP condition SCL SDA |
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