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FCAS20DN60BB Datasheet(PDF) 11 Page - Fairchild Semiconductor |
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FCAS20DN60BB Datasheet(HTML) 11 Page - Fairchild Semiconductor |
11 / 14 page 11 www.fairchildsemi.com FCAS20DN60BB Rev. A Note: 5. RC coupling at each input (parts shown dotted) might change depending on the PWM control scheme used in the application and the wiring impedance of the application’s printed circuit board. The input signal section integrates 3.3k Ω(typ.) pull-down resistor. Therefore, when using an external filtering resistor, please pay attention to the signal voltage drop at input terminal. 6. The logic input is compatible with standard CMOS or LSTTL outputs. Figure 10. Recommended CPU I/O Interface Circuit Note: 1) The ceramic capacitor placed between VCC-COM should be over 1uF and mounted as close to the pins of the SPM as possible. Figure 11. Recommended Bootstrap Operation Circuit and Parameters CPU COM 5V-Line 1nF Ω 4.7k VFO Ω 100 1nF SRM Module R PF= C PF= IN (H) IN (L) 15V-Line 18uF 0.1uF 1000uF 1uF SRM module Output P N This Value depend on PWM Control Algorithm Vcc IN COM VB HO VS Vcc IN COM OUT V SL |
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