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LC5256MB-4F484C Datasheet(PDF) 2 Page - Lattice Semiconductor |
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LC5256MB-4F484C Datasheet(HTML) 2 Page - Lattice Semiconductor |
2 / 92 page Lattice Semiconductor ispXPLD 5000MX Family Data Sheet 2 Figure 1. ispXPLD 5000MX Block Diagram Introduction The ispXPLD 5000MX family represents a new class of device, referred to as the eXpanded Programmable Logic Devices (XPLDs). These devices extend the capability of Lattice’s popular SuperWIDE ispMACH 5000 architecture by providing flexible memory capability. The family supports single- or dual-port SRAM, FIFO, and ternary CAM operation. Extra logic has also been included to allow efficient implementation of arithmetic functions. In addition, sysCLOCK PLLs and sysIO interfaces provide support for the system-level needs of designers. The devices provide designers with a convenient one-chip solution that provides logic availability at boot-up, design security, and extreme reconfigurability. The use of advanced process technology provides industry-leading perfor- mance with combinatorial propagation delay as low as 4.0ns, 2.8ns clock-to-out delay, 2.2ns set-up time, and oper- ating frequency up to 300MHz. This performance is coupled with low static and dynamic power consumption. The ispXPLD 5000MX architecture provides predictable deterministic timing. The availability of 3.3, 2.5 and 1.8V versions of these devices along with the flexibility of the sysIO interface helps users meet the challenge of today’s mixed voltage designs. Inputs can be safely driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. Boundary scan testability further eases inte- gration into today’s complex systems. A variety of density and package options increase the likelihood of a good fit for a particular application. Table 1 shows the members of the ispXPLD 5000MX family. Architecture The ispXPLD 5000MX devices consist of Multi-Function Blocks (MFBs) interconnected with a Global Routing Pool. Signals enter and leave the device via one of four sysIO banks. Figure 1 shows the block diagram of the ispXPLD ISP Port Global Routing Pool (GRP) sysCLOCK PLL 0 sysCLOCK PLL 1 sysIO Bank 0 MFB MFB MFB MFB VCCO3 VREF3 VREF2 VCCO2 GCLCK3 GCLK2 RESET GOE0 GOE1 sysIO Bank 1 sysIO Bank 3 sysIO Bank 2 MFB MFB MFB MFB VCCO0 VCCO1 VCCP VREF0 VREF1 GCLCK0 GNDP GCLK1 Optional sysCONFIG Interface |
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