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TPS720XX Datasheet(PDF) 11 Page - Texas Instruments |
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TPS720XX Datasheet(HTML) 11 Page - Texas Instruments |
11 / 22 page APPLICATION INFORMATION INTERNAL CURRENT LIMIT INPUT AND OUTPUT CAPACITOR INRUSH CURRENT LIMIT BOARD LAYOUT RECOMMENDATIONS TO TPS720xx www.ti.com ................................................................................................................................................ SBVS100C – JUNE 2008 – REVISED SEPTEMBER 2008 ground connection for the output capacitor should be The TPS720xx belongs to a family of new generation connected directly to the GND pin of the device. High LDO regulators that use innovative circuitry to equivalent series resistance (ESR) capacitors may achieve ultra-wide bandwidth and high loop gain, degrade PSRR. The BIAS pin draws very little current resulting in extremely high PSRR (up to 1MHz) at and can be routed as a signal (make sure to shield it very low headroom (VIN – VOUT). The implementation from high-frequency coupling). of the BIAS pin on the TPS720xx vastly improves efficiency of low VOUT applications by allowing the use of a preregulated, low-voltage input supply. The TPS720xx supports a novel feature in which the The TPS720xx internal current limits help protect the output of the LDO regulates under light loads regulator during fault conditions. During current limit, (<500 µA) when the IN pin is left floating. The the output sources a fixed amount of current that is light-load drive current is sourced from VBIAS under largely independent of output voltage. In such a case, this condition. This feature is particularly useful in the output voltage is not regulated, and is power-saving applications where the dc/dc converter VOUT = ILIMIT × RLOAD. The NMOS pass transistor connected to the IN pin is disabled but the LDO is still dissipates (VIN – VOUT) × ILIMIT until thermal shut down required to regulate the voltage to a light load. These is triggered and the device is turned off. As the features, combined with low noise, low ground pin device cools down, it is turned on by the internal current, and ultra-small packaging, make this device thermal shutdown circuit. If the fault condition ideal for portable applications. This family of continues, the device cycles between current limit regulators offers sub-bandgap output voltages, and thermal shutdown. See the Thermal Information current limit and thermal protection, and is fully section for more details. specified from –40°C to +125°C. The NMOS pass element in the TPS720xx has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This REQUIREMENTS current is not limited, so if extended reverse voltage Although an input capacitor is not required for stability operation is anticipated, external limiting to 5% of on the IN pin, it is good analog design practice to rated output current is recommended. connect a 0.1 µF to 1.0µF low equivalent series resistance (ESR) capacitor across the IN pin input supply near the regulator. This capacitor counteracts The TPS720xx family of LDO regulators implement a reactive input sources and improves transient novel inrush current-limit circuit architecture: the response, noise rejection, and ripple rejection. A current drawn through the IN pin is limited to a finite higher-value capacitor may be necessary if large, fast value. This IINRUSHLIMIT charges the output to its final rise-time load transients are anticipated, or if the voltage. All the current drawn through VIN goes to device is located close to the power source. If source charge the output capacitance when the load is impedance is not sufficiently low, a 0.1 µF input disconnected. The following equation shows the capacitor may be necessary to ensure stability. inrush current limit performed by the circuit: The BIAS pin does not require an input capacitor IINRUSHLIMIT(A) = COUT(µF) × 0.0454545(V/µs) + because it does not source high currents. However, if ILOAD(A) (1) source impedance is not sufficiently low, a small 0.1 µF bypass capacitor is recommended. Assuming a COUT of 2.2µF with the load disconnected (that is, ILOAD = 0) the IINRUSHLIMIT is calculated to be The TPS720xx is designed to be stable with standard 100mA. The inrush current charges the LDO output ceramic capacitors with values of 2.2 µF or larger at capacitor. If the output of the LDO regulates to 1.3V, the output. X5R- and X7R-type capacitors are best then the LDO charges the output capacitor to the final because they have minimal variation in value and output value in approximately 28.6 µs. ESR over temperature. Maximum ESR should be less than 250m Ω. Another consideration is when a load is connected to the output of an LDO. The connected load tries to steer a portion of the current away from VOUT. The TPS720xx inrush current-limit circuit employs a new IMPROVE PSRR AND NOISE PERFORMANCE technique that supplies not only the IINRUSHLIMIT, but To improve ac performance such as PSRR, output also the additional current needed by the load. If noise, and transient response, it is recommended that ILOAD = 350mA, then the IINRUSHLIMIT calculates to be the board be designed with separate ground planes approximately 450mA (from Equation 1). for VIN and VOUT, with the ground plane connected only at the GND pin of the device. In addition, the Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 11 |
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