8

Notes (Read Cycle)

1. WE are high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

3.

t

4. At any given temperature and voltage condition

t

device.

5. Transition is measured + 200mV from steady state voltage with load. This parameter is sampled and not 100% tested.

7. Address valid prior to coincident with CE transition Low.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write

cycle.

9. For test conditions, see AC Test Condition, Figure A.

Timing Waveform of Read Cycle 1 (Address Controlled)

t

RC

t

AA

t

OH

Data Valid

Address

Data Out

Timing Waveform of Read Cycle 2

t

OHZ

t

RC

t

OLZ

t

ACE

t

LZ(4,5)

CE

Previous Data Valid

Address

t

OH

t

AA

t

OE

t

BA

t

BLZ(4,5)

t

BHZ(3,4,5)

t

HZ(3,4,5)

(BLE/BHE)

OE

Data Out

Data Valid

V62C3162048L(L)

REV. 1.2 May 2001 V62C3162048L(L)