10

Notes (Write Cycle)

1.

All write timing is referenced from the last valid address to the first transition address.

2.

A write occurs during the overlap of a low CE and WE. A write begins at the latest transition among CE and WE going

low: A write ends at the earliest transition among CE going high and WE going high.

t

of write to the end of write.

3.

t

4.

t

5.

t

6.

If OE, CE and WE are in the Read Mode during this period, the I/O pins are in the output Low-Z state.

Inputs of opposite phase of the output must not be applied because bus contention can occur.

7.

For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and

write cycle.

8.

If CE goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state.

9.

10. When CE is low: I/O pins are in the outputs state. The input signals in the opposite phase leading to the output should

not be applied.

11. For test conditions, see AC Test Condition, Figure A.

V62C3162048L(L)

REV. 1.2 May 2001 V62C3162048L(L)