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LCMXO640LUTSE-4FTN324I Datasheet(PDF) 7 Page - Lattice Semiconductor |
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LCMXO640LUTSE-4FTN324I Datasheet(HTML) 7 Page - Lattice Semiconductor |
7 / 95 page 2-4 Architecture Lattice Semiconductor MachXO Family Data Sheet There are 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent Slice/PFU). There are 7 outputs: 6 to the routing and one to the carry-chain (to the adjacent Slice/PFU). Table 2-1 lists the sig- nals associated with each Slice. Figure 2-5. Slice Diagram Table 2-1. Slice Signal Descriptions Function Type Signal Names Description Input Data signal A0, B0, C0, D0 Inputs to LUT4 Input Data signal A1, B1, C1, D1 Inputs to LUT4 Input Multi-purpose M0/M1 Multipurpose Input Input Control signal CE Clock Enable Input Control signal LSR Local Set/Reset Input Control signal CLK System Clock Input Inter-PFU signal FCIN Fast Carry In 1 Output Data signals F0, F1 LUT4 output register bypass signals Output Data signals Q0, Q1 Register Outputs Output Data signals OFX0 Output of a LUT5 MUX Output Data signals OFX1 Output of a LUT6, LUT7, LUT8 2 MUX depending on the Slice Output Inter-PFU signal FCO Fast Carry Out 1 1. See Figure 2-4 for connection details. 2. Requires two PFUs. LUT4 & CARRY LUT4 & CARRY Slice A0 B0 C0 D0 FF/ Latch OFX0 F0 Q0 A1 B1 C1 D1 CI CI CO CO F SUM CE CLK LSR FF/ Latch OFX1 F1 Q1 Fast Connection to I/O Cell* F SUM D D M1 From Adjacent Slice/PFU To Adjacent Slice/PFU Fast Connection to I/O Cell* LUT Expansion Mux M0 OFX0 From Routing To Routing Control Signals selected and inverted per Slice in routing Notes: Some inter-Slice signals are not shown. * Only PFUs at the edges have fast connections to the I/O cell. |
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