Electronic Components Datasheet Search |
|
ALD750DKCT Datasheet(PDF) 1 Page - Abracon Corporation |
|
ALD750DKCT Datasheet(HTML) 1 Page - Abracon Corporation |
1 / 2 page Frequency Range Operating Temperature Storage Temperature Overall Frequency Stability Supply Voltage (Vdd) Linearity Jitter (12KHz - 20MHz) ABRACON IS ABRACON IS ISO 9001 / QS 9000 ISO 9001 / QS 9000 CERTIFIED CERTIFIED ABRACON IS ISO 9001 / QS 9000 CERTIFIED 30332 Esperanza, Rancho Santa Margarita, California 92688 tel 949-546-8000 | fax 949-546-8001 | www.abracon.com CERAMIC SMD CRYSTAL CLOCK OSCILLATOR CERAMIC SMD CRYSTAL CLOCK OSCILLATOR CERAMIC SMD CRYSTAL CLOCK OSCILLATOR ||||||||||||||| ALD SERIES STANDARD SPECIFICATIONS: APPLICATIONS: • SONET, xDSL • SDH, CPE • STB FEATURES: • Based on a proprietary digital multiplier • Tri-State Output • Low Phase Jitter • 156.25MHz, 187.5MHz, and 212.5MHz applications • 2.5V to 3.3V +/- 5% operation • Ceramic SMD, low profile package PARAMETERS PECL 750 KHz to 800 MHz 0°C to + 70°C (see options) - 40°C to + 85°C ± 50 ppm max. (see options) 2.5V to 3.3 Vdc ± 5% 5% typ, 10% max. RMS phase jitter 3pS typ. < 5pS max. period jitter < 35pS peak to peak Phase Noise Tri-State Function -109 dBc/Hz @ 1kHz Offset from 622.08MHz -110 dBc/Hz @ 10kHz Offset from 622.08MHz -109 dBc/Hz @ 100kHz Offset from 622.08MHz “1” (VIH > 0.7*VDD) or open: Oscillation/ “0” (VIH > 0.3*VDD) No Oscillation/Hi Z 5.08 x 7.0 x 1.8mm Supply Current (IDD) Symmetry (Duty Cycle) Output Logic High Output Logic Low Clock Rise time (tr) @ 20/80% Clock Fall time (tf) @ 80/20% 80mA (Fo < 155.52MHz), 100mA (Fo < 155.52MHz) 45% min, 50% typical, 55% max. VDD -1.025V min, VDD -0.880V max. VDD -1.810V min, VDD -1.620V max. 1.5ns max, 0.6nSec typical 1.5ns max, 0.6nSec typical LVDS Supply Current (IDD) [Fout = 212.50MHz] Output Clock Duty Cycle @ 1.25V Output Differential Voltage (VOD) VDD Magnitude Change ( ∆VOD) Output High Voltage Output Low Voltage Offset Voltage [RL = 100 Ω] Offset Magnitude Voltage[RL = 100 Ω] Power-off Leakage (IOXD) [Vout=VDD or GND, VDD=0V] Differential Clock Rise Time (tr) [RL=100 Ω, CL=10pF] Differential Clock Fall Time (tf) [RL=100 Ω, CL=10pF] CMOS Output Clock Rise/ Fall Time [10%~90% VDD with 10pF load] Output Clock Duty Cycle [Measured @ 50% VDD] 1.6ns max, 1.2ns typical 45% min, 50% typical, 55% max 60mA max, 55mA typical. 45% min, 50% typical, 55% max 247mV min, 355mV typical, 454mV max -50mV min, 50mV max VOH = 1.6V max, 1.4V typical VOL = 0.9V min, 1.1V typical VOS = 1.125V min, 1.2V typical, 1.375V max ∆VOS = 0mV min, 3mV typical, 25mV max ±10 µA max, ±1µA typical 0.2ns min, 0.5ns typical, 0.7ns max 0.2ns min, 0.5ns typical, 0.7ns max : PRELIMINARY |
Similar Part No. - ALD750DKCT |
|
Similar Description - ALD750DKCT |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |