UCC1895

UCC2895

UCC3895

SLUS157L − DECEMBER 1999 − REVISED APRIL 2008

3

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ABSOLUTE MAXIMUM RATINGS

−40

°C ≤ TA ≤ 85°C, all voltage values are with respect to the network ground terminal unless otherwise noted. (2)

UCC2895N

UNIT

Supply voltage

(IDD < 10 mA)

17

V

Supply current

30

Reference current

15

mA

Output crrent

100

mA

Analog inputs

EAP, EAN, EAOUT, RAMP, SYNC, ADS, CS, SS/DISB

−0.3 V to REF+0.3 V

V

Drive outputs

OUTA, OUTB, OUTC, OUTD

−0.3 V to VCC + 0.3 V

V

Power dissipation at TA =25°C

DW−20 package

650

mW

Power dissipation at TA =25°C

N−20 package

1

W

Storage temperature range, Tstg

−65 to 150

Junction temperature range, TJ

−55 to 150

°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

300

C

(2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond those indicated under ”recommended operating conditions” is

not implied. Exposure to Absolute Maximum Rated conditions for extended periods may affect device reliability

MIN

TYP

MAX

UNIT

Supply voltage, VDD

9

16.5

V

Supply voltage bypass capacitor, VDD(1)

10 x CREF

F

Reference bypass capacitor, CREF(2)

0.1

1.0

µF

Timing capacitor, CT (for 500 kHz switching frequency)

220

pF

Timing resistor, RT (for 500 kHz switching frequency)

82

k

Ω

Delay resistor RDEL_AB, RDEL_CD

2.5

40

k

Ω

Operating junction temperature, TJ(4)

−55

125

°C

(1) The VDD capacitor should be a low ESR, ESL ceramic capacitor located directly across the VDD and PGND pins. A larger bulk capacitor should

belocated as physically close as possible to the VDD pins.

(2) The VREF capacitor should be a low ESR, ESL ceramic capacitor located directly across the REF and GND pins. If a larger capacitor is desired

for the VREF then it should be located near the VREF cap and connected to the VREF pin with a resistor of 51 Ω or greater. The bulk capacitor on

VDD must be a factor of 10 greater than the total VREF capacitance.

(3) It is recommended that there be a single point grounded between GND and PGND directly under the device. There should be a seperate ground

plane associated with the GND pin and all components associated with pins 1 through 12 plus 19 and 20 be located over this ground plane. Any

connections associated with these pins to ground should be connected to this ground plane.

(4) It is not recommended that the device operate under conditions beyond those specified in this table for extended periods of time.