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UCC2895Q Datasheet(PDF) 6 Page - Texas Instruments |
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UCC2895Q Datasheet(HTML) 6 Page - Texas Instruments |
6 / 25 page UCC1895 UCC2895 UCC3895 SLUS157L − DECEMBER 1999 − REVISED APRIL 2008 6 www.ti.com ELECTRICAL CHARACTERISTICS VDD = 12 V, RT = 82 kΩ, CT = 220 pF, RDELAB = 10 kΩ, RDELCD = 10 kΩ, CREF = 0.1 µF, CVDD = 0.1 µF and no load on the outputs, TA = TJ. TA = 0°C to 70°C for UCC3895x, TA = −40°C to 85°C for UCC2895x and TA = 55°C to 125°C for the UCC1895x. (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS PWM COMPARATOR EAOUT to RAMP input offset voltage RAMP = 0 V, DELAB=DELCD=REF 0.72 0.85 1.05 V Minimum phase shift(2) (OUTA to OUTC, OUTB to OUTD) RAMP = 0 V EAOUT = 650 mV .0% .85% 1.4% tDELAY Delay(3) (RAMP to OUTC, RAMP to OUTD) 0 V < RAMP < 2.5 V, EAOUT = 1.2 V, DELAB=DELCD=REF 70 120 ns IR(bias) RAMP bias current RAMP < 5 V, CT = 2.2 V −5 5 µA IR(sink) RAMP sink current RAMP = 5 V, CT = 2.6 V 12 19 mA TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION ADS 11 I Adaptive delay set. Sets the ratio between the maximum and minimum programmed output delay dead time. CS 12 I Current sense input for cycle-by-cycle current limiting and for over-current comparator. CT 7 I Oscillator timing capacitor for programming the switching frequency. The UCC3895’s oscillator charges CT via a programmed current. DELAB 9 I Delay programming between complementary outputs. DELAB programs the dead time between switching of output A and output B. DELCD 10 I Delay programming between complementary outputs. DELCD programs the dead time between switching of output C and output D. EAOUT 2 I/O Error amplifier output. EAP 20 I Non-inverting input to the error amplifier. Keep below 3.6 volts for proper operation. EAN 1 I Inverting input to the error amplifier. Keep below 3.6 volts for proper operation. GND 5 − Chip ground for all circuits except the output stages. OUTA 18 O OUTB 17 O The four outputs are 100-mA complementary MOS drivers, and are optimized to drive FET driver circuits OUTC 14 O The four outputs are 100-mA complementary MOS drivers, and are optimized to drive FET driver circuits such as UCC27424 or gate drive transformers. OUTD 13 O PGND 16 − Output stage ground. RAMP 3 I Inverting input of the PWM comparator. REF 4 O 5 V, ±1.2%, 5 mA voltage reference. For best performance, bypass with a 0.1-µF low ESR, low ESL capacitor to ground. Do not use more than 1.0 µF of total capacitance on this pin. RT 8 I Oscillator timing resistor for programming the switching frequency. SS/DISB 19 I Soft-start/disable. This pin combines the two independent functions. SYNC 6 I/O Oscillator synchronization. This pin is bidirectional. VDD 15 I Power supply input pin. VDD must be bypassed with a minimum of a 1.0- µF low ESR, low ESL capacitor to ground. The addition of a 10− µF low ESR, low ESL between VDD and PGND is recommended. |
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