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LFE220SE-7F256I Datasheet(PDF) 6 Page - Lattice Semiconductor |
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LFE220SE-7F256I Datasheet(HTML) 6 Page - Lattice Semiconductor |
6 / 386 page 2-3 Architecture Lattice Semiconductor LatticeECP2/M Family Data Sheet PFU Blocks The core of the LatticeECP2/M device consists of PFU blocks, which are provided in two forms, the PFU and PFF. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform Logic, Arithmetic and ROM functions. Except where necessary, the remain- der of this data sheet will use the term PFU to refer to both PFU and PFF blocks. Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-3. All the interconnec- tions to and from PFU blocks are from routing. There are 50 inputs and 23 outputs associated with each PFU block. Figure 2-3. PFU Diagram Slice Slice 0 through Slice 2 contain two LUT4s feeding two registers, whereas Slice 3 contains two LUT4s only. For PFUs, Slice 0 and Slice 2 can also be configured as distributed memory, a capability not available in the PFF. Table 2-1 shows the capability of the slices in both PFF and PFU blocks along with the operation modes they enable. In addition, each PFU contains some logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions (programmable as synchro- nous/asynchronous), clock select, chip-select and wider RAM/ROM functions. Figure 2-4 shows an overview of the internal logic of the slice. The registers in the slice can be configured for positive/negative and edge triggered or level sensitive clocks. Table 2-1. Resources and Modes Available per Slice Slices 0, 1 and 2 have 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent slice or PFU). There are seven outputs: six to routing and one to carry-chain (to the adjacent PFU). Slice 3 has 13 input signals from routing and four signals to routing. Table 2-2 lists the signals associated with Slice 0 to Slice 2. Slice PFU BLock PFF Block Resources Modes Resources Modes Slice 0 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM Slice 1 2 LUT4s and 2 Registers Logic, Ripple, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM Slice 2 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM Slice 3 2 LUT4s Logic, ROM 2 LUT4s Logic, ROM Slice 0 LUT4 & CARRY LUT4 & CARRY D D Slice 1 LUT4 & CARRY LUT4 & CARRY Slice 2 LUT4 & CARRY LUT4 & CARRY From Routing To Routing Slice 3 LUT4 LUT4 D D D D FF FF FF FF FF FF |
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