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LX128EVCFN10035 Datasheet(PDF) 9 Page - Lattice Semiconductor

Part # LX128EVCFN10035
Description  High Performance Interfacing and Switching
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

LX128EVCFN10035 Datasheet(HTML) 9 Page - Lattice Semiconductor

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Lattice Semiconductor
ispGDX2 Family Data Sheet
9
Table 3. ispGDX2 Supported I/O Standards
The dedicated inputs support a subset of the sysIO standards indicated in Table 4. These inputs are associated
with a bank consistent with their location.
Table 4. I/O Standards Supported by Dedicated Inputs
For more information on the sysIO capability, please refer to Lattice technical note number TN1000, sysIO Design
and Usage Guidelines.
sysCLOCK PLL
The sysCLOCK PLL circuitry consists of Phase-Lock Loops (PLLs) along the various dividers and reset and feed-
back signals associated with the PLLs. This feature gives the user the ability to synthesize clock frequencies and
generate multiple clock signals for routing within the device. Furthermore, it can generate clock signals that are
deskewed either at the board level or the device level. Figure 6 shows the ispGDX2 PLL block diagram.
Each PLL has a set of PLL_RST, PLL_FBK and PLL_LOCK signals. In order to facilitate the multiply and divide
capabilities of the PLL, each PLL has associated dividers. The M divider is used to divide the clock signal, while the
sysIO Standard
Nominal VCCO
Nominal VREF
Nominal VTT
LVCMOS 3.3
3.3V
LVCMOS 2.5
2.5V
LVCMOS 1.8
1.8V
LVTTL
3.3V
PCI 3.3
3.3V
PCI -X
3.3V
AGP-1X
3.3V
SSTL3 class I & II
3.3V
1.5V
1.5V
SSTL2 class I & II
2.5V
1.25V
1.25V
CTT 3.3
3.3V
1.5V
1.5V
CTT 2.5
2.5V
1.25V
1.25V
HSTL class I
1.5V
0.75V
0.75V
HSTL class III
1.5V
0.9V
0.75V
HSTL class IV
1.5V
0.9V
1.5V
GTL+
1.8/2.5/3.3V
1.0V
1.5V
LVPECL
1, 2, 3
3.3V
LVDS
2.5/3.3V
Bus-LVDS
2.5/3.3V
1. LVPECL drivers require three resistor pack (see Figure 17).
2. Depending on the driving LVPECL output specification, GDX2 LVPECL input driver may require terminating resistors.
3. For additional information on LVPECL refer to Lattice technical note number TN1000, sysIO Design and Usage Guidelines.
LVCMOS
LVDS
All other ASIC I/Os
Global OE Pins
Yes
No
Yes
2
Global MUX Select Pins
Yes
No
Yes
2
Resetb
Yes
No
Yes
2
Global Clock/Clock Enables
Yes
Yes
Yes
2
ispJTAG™ Port
Yes
1
No
No
TOE
Yes
No
No
1. LVCMOS as defined by the VCCJ pin voltage.
2. No PCI clamp.


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