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LX64BCFN20832 Datasheet(PDF) 11 Page - Lattice Semiconductor

Part # LX64BCFN20832
Description  High Performance Interfacing and Switching
Download  72 Pages
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

LX64BCFN20832 Datasheet(HTML) 11 Page - Lattice Semiconductor

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Lattice Semiconductor
ispGDX2 Family Data Sheet
11
Figure 7. I/O Pin Connection to the sysCLOCK PLL
1
GDX Block
GRP
GCLK_IN
PLL_RST
PLL_FBK
PLL_LOCK
CLK_OUT
From Adjacent_PLL
Input Clock
(M) Divider
÷ 1 to 32
--------------------
To Adjacent_PLL
Clock Net
GCLK_IN
Input
Reg/
Latch
Output
Reg/
Latch
Delay
Control Array
(from selected blocks)
1. Some pins are shared. See Logic Signal Connections Table for details.
Resetb (0)
Programmable
+ Delay
Programmable
- Delay
PLL (n)
Post-scalar
(V) Divider
÷
1, 2, 4, 8,
16, 32
Feedback
Divider (N)
x 1 to 32
Clock
(K) Divider
÷
2, 4, 8,
16, 32


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