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LM3S600-IQC25-B0T Datasheet(PDF) 5 Page - Bookham, Inc. |
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LM3S600-IQC25-B0T Datasheet(HTML) 5 Page - Bookham, Inc. |
5 / 378 page 10.5 Register Descriptions .............................................................................................................. 195 11 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 216 11.1 Block Diagram ........................................................................................................................ 217 11.2 Functional Description ............................................................................................................. 217 11.2.1 Transmit/Receive Logic ........................................................................................................... 217 11.2.2 Baud-Rate Generation ............................................................................................................. 218 11.2.3 Data Transmission .................................................................................................................. 219 11.2.4 FIFO Operation ....................................................................................................................... 219 11.2.5 Interrupts ................................................................................................................................ 219 11.2.6 Loopback Operation ................................................................................................................ 220 11.3 Initialization and Configuration ................................................................................................. 220 11.4 Register Map .......................................................................................................................... 221 11.5 Register Descriptions .............................................................................................................. 222 12 Synchronous Serial Interface (SSI) ................................................................................ 254 12.1 Block Diagram ........................................................................................................................ 254 12.2 Functional Description ............................................................................................................. 254 12.2.1 Bit Rate Generation ................................................................................................................. 255 12.2.2 FIFO Operation ....................................................................................................................... 255 12.2.3 Interrupts ................................................................................................................................ 255 12.2.4 Frame Formats ....................................................................................................................... 256 12.3 Initialization and Configuration ................................................................................................. 263 12.4 Register Map .......................................................................................................................... 264 12.5 Register Descriptions .............................................................................................................. 265 13 Inter-Integrated Circuit (I2C) Interface ............................................................................ 291 13.1 Block Diagram ........................................................................................................................ 291 13.2 Functional Description ............................................................................................................. 291 13.2.1 I2C Bus Functional Overview .................................................................................................... 292 13.2.2 Available Speed Modes ........................................................................................................... 294 13.2.3 Interrupts ................................................................................................................................ 295 13.2.4 Loopback Operation ................................................................................................................ 295 13.2.5 Command Sequence Flow Charts ............................................................................................ 296 13.3 Initialization and Configuration ................................................................................................. 302 13.4 I2C Register Map ..................................................................................................................... 303 13.5 Register Descriptions (I2C Master) ........................................................................................... 304 13.6 Register Descriptions (I2C Slave) ............................................................................................. 317 14 Analog Comparators ....................................................................................................... 326 14.1 Block Diagram ........................................................................................................................ 327 14.2 Functional Description ............................................................................................................. 327 14.2.1 Internal Reference Programming .............................................................................................. 329 14.3 Initialization and Configuration ................................................................................................. 330 14.4 Register Map .......................................................................................................................... 330 14.5 Register Descriptions .............................................................................................................. 331 5 October 01, 2007 Preliminary LM3S600 Microcontroller |
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