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STLS2F01 Datasheet(PDF) 10 Page - STMicroelectronics |
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STLS2F01 Datasheet(HTML) 10 Page - STMicroelectronics |
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10 / 48 page  Interface description STLS2F01 10/48 2.3 DDR2 SDRAM interface signal components The STLS2F01 includes a built-in memory controller fully compatible with DDR2 SDRAM industry standard (JESD79-2B). These signals include: ● 72-bit bidirectional data bus (ECC included) ● 9-bit bidirectional data strobe differential signal (ECC included) ● 9-bit data mask signal (ECC included) ● 15-bit address bus ● 7-bit bank and chip select signal ● 6-bit differential clock ● 4-bit clock enable ● 3-bit command bus ● 4-bit delay sample input/output signal ● 4-bit ODT (on die termination) signal The STLS2F01 DDR2 SDRAM controller signals are listed in Table 3. Table 3. DDR2 SDRAM controller interface signals Name Input/output Description DDR2_DQ[63:0] IO DDR2 SDRAM data bus DDR2_CB[7:0] IO DDR2 SDRAM data ECC data bus DDR2_DQSp[8:0] IO DDR2 SDRAM data strobe (ECC included) DDR2_DQSn[8:0] IO DDR2 SDRAM data strobe (ECC included) DDR2_DQM[8:0] O DDR2 SDRAM data mask (ECC included) DDR2_A[14:0] O DDR2 SDRAM address bus DDR2_BA[2:0] O DDR2 SDRAM bank address signal DDR2_WEn O DDR2 SDRAM write enable DDR2_CASn O DDR2 SDRAM column select enable DDR2_RASn O DDR2 SDRAM row select enable DDR2_SCSn[3:0] O DDR2 SDRAM chip select DDR2_CKE[3:0] O DDR2 SDRAM clock enable DDR2_CKp[5:0] O DDR2 SDRAM phase clock output DDR2_CKn[5:0] O DDR2 SDRAM phase inversion clock output DDR2_GATEI[3:0] I DDR2 SDRAM delay sample input signal DDR2_GATEO[3:0] O DDR2 SDRAM delay sample output signal DDR2_ODT[3:0] O DDR2 SDRAM on-die termination signal |
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