Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

LX64VIFN4843 Datasheet(PDF) 3 Page - Lattice Semiconductor

Part # LX64VIFN4843
Description  High Performance Interfacing and Switching
Download  72 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

LX64VIFN4843 Datasheet(HTML) 3 Page - Lattice Semiconductor

  LX64VIFN4843 Datasheet HTML 1Page - Lattice Semiconductor LX64VIFN4843 Datasheet HTML 2Page - Lattice Semiconductor LX64VIFN4843 Datasheet HTML 3Page - Lattice Semiconductor LX64VIFN4843 Datasheet HTML 4Page - Lattice Semiconductor LX64VIFN4843 Datasheet HTML 5Page - Lattice Semiconductor LX64VIFN4843 Datasheet HTML 6Page - Lattice Semiconductor LX64VIFN4843 Datasheet HTML 7Page - Lattice Semiconductor LX64VIFN4843 Datasheet HTML 8Page - Lattice Semiconductor LX64VIFN4843 Datasheet HTML 9Page - Lattice Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 3 / 72 page
background image
Lattice Semiconductor
ispGDX2 Family Data Sheet
3
The sysIO interfaces provide system-level performance and integration. These I/Os support various modes of
LVCMOS/LVTTL and support popular high-speed standard interfaces such as GTL+, PCI-X, HSTL, SSTL, LVDS
and Bus-LVDS. The sysHSI Blocks further extend this capability by providing high speed serial data transfer capa-
bility.
Devices in the family can operate at 3.3V, 2.5V or 1.8V core voltages and can be programmed in-system via an
IEEE 1149.1 interface that is compliant with the IEEE 1532 standard. Voltages required for the I/O buffers are inde-
pendent of the core voltage supply. This further enhances the flexibility of this family in system designs.
Typical applications for the ispGDX2 include multi-port multi-processor interfaces, wide data and address bus mul-
tiplexing, programmable control signal routing and programmable bus interfaces. Table 1 shows the members of
the ispGDX2 family and their key features.
Architecture
The ispGDX2 devices consist of GDX Blocks interconnected by a Global Routing Pool (GRP). Signals interface
with the external system via sysIO banks. In addition, each GDX Block is associated with a FIFO and a sysHSI
Block to facilitate the transfer of data on- and off-chip. Figure 1 shows the ispGDX2 block diagram. Each GDX
Block can be individually configured in one of four modes:
• Basic (No FIFO or SERDES)
• FIFO Only
• SERDES Only
• SERDES and FIFO
Each sysIO bank has its own I/O power supply and reference voltage. Designers can use any output standard
within a bank that is compatible with the power supply. Any input standard may be used, providing it is compatible
with the reference voltage. The banks are independent.
Global Routing Pool (GRP)
The ispGDX2 architecture is organized into GDX Blocks, which are connected via a Global Routing Pool. The inno-
vative GRP is optimized for routability, flexibility and speed. All the signals enter via the GDX Block. The block sup-
plies these either directly or in registered form to the GRP. The GRP routes the signals to different blocks, and
provides separate data and control routing. The data path is optimized to achieve faster speed and routing flexibility
for nibble oriented signals. The control routing is optimized to provide high-speed bit oriented routing of control sig-
nals.
There are some restrictions on the allocation of pins for optimal bus routing. These restrictions are considered by
the software in the allocation of pins.
GDX Block
The blocks are organized in a “block” (nibble) manner, with each GDX Block providing data flow and control logic
for 16 I/O buffers. The data flow is organized as four nibbles, each nibble containing four Multiplexer Register
Blocks (MRBs). Data for the MRBs is provided from 64 lines from the GRP. Figure 2 illustrates the groups of signals
going into and out of a GDX Block.
Control signals for the MRBs are provided from the Control Array. The Control Array receives the 32 signals from
the GRP and generates 16 control signals: eight MUX Select, four Clock/Clock Enable, two Set/Reset and two Out-
put Enable. Each nibble is controlled via two MUX select signals. The remaining control signals go to all the MRBs.
Besides the control signals from the Control Array, the following global signals are available to the MRBs in each
GDX Block: four Clock/Clock Enable, one reset/preset, one power-on reset, two of four MUX select (two of two in
64 I/O), four Output Enable (two in 64 I/O) and Test Out Enable (TOE).


Similar Part No. - LX64VIFN4843

ManufacturerPart #DatasheetDescription
logo
Lattice Semiconductor
LX64V LATTICE-LX64V Datasheet
654Kb / 75P
   IC SWITCH DIGITAL 208FBGA
June 2010
LX64V-3F100C LATTICE-LX64V-3F100C Datasheet
899Kb / 75P
   ispGDX2??Device Datasheet
LX64V-3F100C LATTICE-LX64V-3F100C Datasheet
654Kb / 75P
   IC SWITCH DIGITAL 208FBGA
June 2010
LX64V-3FN100C LATTICE-LX64V-3FN100C Datasheet
899Kb / 75P
   ispGDX2??Device Datasheet
LX64V-3FN100C LATTICE-LX64V-3FN100C Datasheet
654Kb / 75P
   IC SWITCH DIGITAL 208FBGA
June 2010
More results

Similar Description - LX64VIFN4843

ManufacturerPart #DatasheetDescription
logo
STMicroelectronics
AN1318 STMICROELECTRONICS-AN1318 Datasheet
63Kb / 9P
   INTERFACING BETWEEN LVDS AND HIGH
logo
ON Semiconductor
AN1568 ONSEMI-AN1568 Datasheet
86Kb / 10P
   Interfacing Between LVDS and ECL
October, 2003 ??Rev. 8
logo
ATMEL Corporation
C51 ATMEL-C51 Datasheet
49Kb / 4P
   CAN Interfacing
logo
Fairchild Semiconductor
AN-5029 FAIRCHILD-AN-5029 Datasheet
232Kb / 6P
   Interfacing Between PECL and LVDS Differential Technologies
logo
Analog Devices
AN-291 AD-AN-291 Datasheet
313Kb / 2P
   Asynchronous clock Interfacing
logo
TAITRON Components Inco...
MMBD4148-193 TAITRON-MMBD4148-193 Datasheet
136Kb / 4P
   High Performance Switching Diode
logo
ON Semiconductor
AND8066 ONSEMI-AND8066 Datasheet
69Kb / 8P
   Interfacing with ECLinPS
May, 2002 ??Rev. 2
logo
Lowpower Semiconductor ...
LP3320 POWER-LP3320 Datasheet
384Kb / 9P
   High Performance, Constant Current Switching
logo
Toshiba Semiconductor
TLP2403 TOSHIBA-TLP2403 Datasheet
233Kb / 12P
   High-Speed Digital Interfacing for Instrumentation and Control Devices Simplex/Multiplex Data Transmission
logo
Active-Semi, Inc
ACT364 ACTIVE-SEMI-ACT364 Datasheet
114Kb / 3P
   High Performance ActivePSR??Primary Switching Regulator
15-Apr-11
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com