OR4E06-1BM680I datasheet(3/152 Pages) LATTICE

Part #	OR4E06-1BM680I

Description	ORCASeries 4 FPGAs

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Manufacturer	LATTICE [Lattice Semiconductor]

Direct Link	http://www.latticesemi.com

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Lattice Semiconductor

3

Data Sheet

May, 2006

ORCA Series 4 FPGAs

Programmable Features (continued)

■

New capability to (de)multiplex I/O signals:

— New double data rate on both input and output at

rates up to 350 MHz (700 MHz effective rate).

— New 2x and 4x downlink and uplink capability per

I/O (i.e., 50 MHz internal to 200 MHz I/O).

■

Enhanced twin-quad programmable function unit

(PFU):

— Eight 16-bit look-up tables (LUTs) per PFU.

— Nine user registers per PFU, one following each

LUT and organized to allow two nibbles to act

independently, plus one extra for arithmetic opera-

tions.

— New register control in each PFU has two inde-

pendent programmable clocks, clock enables,

local set/reset, and data selects.

— New LUT structure allows ﬂexible combinations of

LUT4, LUT5, new LUT6, 4 to 1 MUX, new

8 to 1 MUX, and ripple mode arithmetic functions

in the same PFU.

— 32 x 4 RAM per PFU, conﬁgurable as single- or

dual-port. Create large, fast RAM/ROM blocks

(128 x 8 in only eight PFUs) using the SLIC

decoders as bank drivers.

— Soft-wired LUTs (SWL) allow fast cascading of up

to three levels of LUT logic in a single PFU

through fast internal routing which reduces routing

congestion and improves speed.

— Flexible fast access to PFU inputs from routing.

— Fast-carry logic and routing to all four adjacent

PFUs for nibble-, byte-wide, or longer arithmetic

functions, with the option to register the PFU

carry-out.

■

Abundant high-speed buffered and nonbuffered rout-

ing resources provide 2x average speed improve-

ments over previous architectures.

■

Hierarchical routing optimized for both local and glo-

bal routing with dedicated routing resources. This

results in faster routing times with predictable and

efﬁcient performance.

■

SLIC provides eight 3-statable buffers, up to 10-bit

decoder, and PAL™-like and-or-invert (AOI) in each

programmable logic cell.

■

Improved built-in clock management with program-

mable phase-locked loops (PPLLs) provide optimum

clock modiﬁcation and conditioning for phase, fre-

quency, and duty cycle from 15 MHz up to 420 MHz.

Multiplication of the input frequency up to 64x, and

division of the input frequency down to 1/64x possi-

ble.

■

New 200 MHz embedded quad-port RAM blocks, two

read ports, two write ports, and two sets of byte lane

enables. Each embedded RAM block can be conﬁg-

ured as:

— 1-512 x 18 (quad-port, two read/two write) with

optional built in arbitration.

— 1-256 x 36 (dual-port, one read/one write).

— 1-1K x 9 (dual-port, one read/one write).

— 2-512 x 9 (dual-port, one read/one write for each).

— 2 RAMS with arbitrary number of words whose

sum is 512 or less by 18 (dual-port, one read/one

write).

— Supports joining of RAM blocks.

— Two 16 x 8-bit content addressable memory

(CAM) support.

— FIFO 512 x 18, 256 x 36, 1K x 9 or dual 512 x 9.

— Constant multiply (8 x 16 or 16 x 8).

— Dual-variable multiply (8 x 8).

■

Embedded 32-bit internal system bus plus 4-bit par-

ity interconnects FPGA logic, microprocessor inter-

face (MPI), embedded RAM blocks, and embedded

standard cell blocks with 100 MHz bus performance.

Included are built-in system registers that act as the

control and status center for the device.

■

Built-in testability:

— Full boundary scan (IEEE

®1149.1 and Draft

1149.2 joint test access group (JTAG)).

— Programming and readback through boundary

scan port compliant to IEEE Draft 1532:D1.7.

— TS_ALL testability function to 3-state all I/O pins.

— New temperature sensing diode.

■

New cycle stealing capability allows a typical 15% to

40% internal speed improvement after ﬁnal place

and route. This feature also enables compliance with

many setup/hold and clock-to-out I/O speciﬁcations

and may provide reduced ground bounce for output

buses by allowing ﬂexible delays of switching output

buffers.

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