 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ORSPI4-3FN1156C Datasheet(PDF) 8 Page - Lattice Semiconductor |
|
||||||||||||||||||||||||||||||
ORSPI4-3FN1156C Datasheet(HTML) 8 Page - Lattice Semiconductor |
|
|
8 / 263 page  Lattice Semiconductor ORCA ORSPI4 Data Sheet 8 • Automatic idle generation – When no data for a given channel is available for transmit – If the receiver on other end of the link is “satisfied” for this channel • Automatic training pattern and idle deletion in receive path • Low-power, high performance ASIC LVDS I/Os compliant with EIA ®-644 – I/O buffers support hot insertion – I/O buffers proven to operate at over 900 MHz rates (Lattice ORLI10G FPSC uses same LVDS buffers) – On-chip center tap termination for common mode noise reduction • Configuration options as suggested in the OIF-SPI4-02.0 standard are supported to configure parameters such as maximum burst size, calendar length, length of training sequence, etc. • Support for three forms of loopback: – High-speed near end loopback which involves looping back data from the high-speed transmit block serial output to the high-speed receive block serial input. All of the logic up to the LVDS buffers is included in the loopback path. The LVDS buffers are bypassed – Far end loopback which involves looping back the 128-bit output data from high-speed receive block to the 128-bit input of the high-speed transmit block. Data is received at the high-speed SPI4 RX interface and transmitted at the SPI4 TX interface. The transmit protocol, receive protocol and DPRAM blocks are bypassed. This works for both static and dynamic alignment modes. – Low-speed near end loopback which excludes the high-speed blocks from the loopback path. This involves sourcing data from the FPGA, looping back the output of the transmit protocol block into the receive protocol block and observing data at the core-FPGA boundary • Support for several SPI4 debug options: – Under software control, DIP-4 errors can be forced by inverting the DIP-4 parity bits – DIP-2 errors can be forced by inverting the DIP-2 parity bits – Eight-bit counters are provided for counting DIP-4 and DIP-2 errors • SPI4 Status Reporting Capabilities: – Status information is reported through status registers. – Most conditions can also cause an alarm (interrupt) to be generated – DIP-4, DIP-2 errors – Deskew error from high-speed RX side – DPRAM Virtual FIFO overruns |
Similar Part No. - ORSPI4-3FN1156C |
|
Similar Description - ORSPI4-3FN1156C |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
