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ORSO42G5-2BM484I Datasheet(PDF) 10 Page - Lattice Semiconductor |
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ORSO42G5-2BM484I Datasheet(HTML) 10 Page - Lattice Semiconductor |
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10 / 153 page  Lattice Semiconductor ORCA ORSO42G5 and ORSO82G5 Data Sheet 10 12.5% of the clock period increments. An automatic input buffer delay compensation mode is available for phase delay. Each PPLL provides two outputs that can have programmable (12.5% steps) phase differences. Embedded Block RAM New 512 x 18 block-port RAM blocks are embedded in the FPGA core to significantly increase the amount of mem- ory and complement the distributed PFU memories. The EBRs include two write ports, two read ports, and two byte lane enables which provide four-port operation. Optional arbitration between the two write ports is available, as well as direct connection to the high-speed system bus. Additional logic has been incorporated to allow significant flexibility for FIFO, constant multiply, and two-variable multiply functions. The user can configure FIFO blocks with flexible depths of 512K, 256K, and 1K including asyn- chronous and synchronous modes and programmable status and error flags. Multiplier capabilities allow a multiply of an 8-bit number with a 16-bit fixed coefficient or vice versa (24-bit output), or a multiply of two 8-bit numbers (16- bit output). On-the-fly coefficient modifications are available through the second read/write port. Two 16 x 8-bit CAMs per embedded block can be implemented in single match, multiple match, and clear modes. The EBRs can also be preloaded at device configuration time. Configuration The FPGAs functionality is determined by internal configuration RAM. The FPGAs internal initialization/configura- tion circuitry loads the configuration data at powerup or under system control. The configuration data can reside externally in an EEPROM or any other storage media. Serial EEPROMs provide a simple, low pin-count method for configuring FPGAs. The RAM is loaded by using one of several configuration modes. Supporting the traditional master/slave serial, master/slave parallel, and asynchronous peripheral modes, Series 4 also utilizes its MicroProcessor Interface and Embedded System Bus to perform both programming and readback. Daisy chaining of multiple devices and partial reconfiguration are also permitted. Other configuration options include the initialization of the embedded-block RAM memories and FPSC memory as well as system bus options and bit stream error checking. Programming and readback through the JTAG (IEEE 1149.2) port is also available meeting In-System Programming (ISP) standards (IEEE 1532 Draft). ORSO42G5 and ORSO82G5 Overview The ORSO42G5 and ORSO82G5 FPSCs provide high-speed backplane transceivers combined with FPGA logic. The ORSO42G5 and ORSO82G5 devices are based on the 1.5V OR4E04 ORCA FPGA and have a 36 x 36 array of Programmable Logic Cells (PLCs). The embedded core, which contains the backplane transceivers, is attached to the right side of the device and is integrated directly into the FPGA array. A top level diagram of the basic chip configuration is shown in Figure 1. |
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