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LAXP2-5E-5QN208E Datasheet(PDF) 5 Page - Lattice Semiconductor |
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LAXP2-5E-5QN208E Datasheet(HTML) 5 Page - Lattice Semiconductor |
5 / 83 page 2-2 Architecture Lattice Semiconductor LA-LatticeXP2 Family Data Sheet Figure 2-1. Simplified Block Diagram, LA-LatticeXP2-17 Device (Top Level) PFU Blocks The core of the LA-LatticeXP2 device is made up of logic blocks in two forms, PFUs and PFFs. PFUs can be pro- grammed to perform logic, arithmetic, distributed RAM and distributed ROM functions. PFF blocks can be pro- grammed to perform logic, arithmetic and ROM functions. Except where necessary, the remainder of this data sheet will use the term PFU to refer to both PFU and PFF blocks. Each PFU block consists of four interconnected slices, numbered Slice 0 through Slice 3, as shown in Figure 2-2. All the interconnections to and from PFU blocks are from routing. There are 50 inputs and 23 outputs associated with each PFU block. On-chip Oscillator Programmable Function Units (PFUs) SPI Port sysCLOCK PLLs Flexible Routing Flash JTAG Port sysIO Buffers, Pre-Engineered Source Synchronous Support sysMEM Block RAM DSP Blocks |
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