Specifications ispLSI 3256E

9

ispLSI 3256E Timing Model

Note: Calculations are based upon timing specifications for the ispLSI 3256E-100L.

GLB Reg

Delay

I/O Pin

(Output)

ORP

Delay

Feedback

4 PT Bypass

20 PT

XOR Delays

Control

PTs

Input

Register

I/O Pin

(Input)

Y0,1,2

Y3,4

D

Q

GRP

GLB Reg Bypass

ORP Bypass

DQ

RST

RE

OE

CK

I/O Reg Bypass

I/O Cell

ORP

GLB

GRP

I/O Cell

#25 - 29

#30

#32

#31

#33 - 35

#41 - 43

#50

#53

#54

#44

#45

Reset

#24

#51

RST

#52

#52

#36

#37 - 40

#48, 49

#46, 47

GOE0,1

TOE

0902/3256E

Derivations of

=

=

=

=

Logic + Reg su - Clock (min)

(

(#24+ #30+ #34) + (#37) - (#24+ #30+ #43)

(2.4 + 2.3 + 4.1) + (0.3) - (2.4 + 2.3 + 3.0)

1.4 ns

=

=

=

=

Clock (max) + Reg h - Logic

(

(#24+ #30+ #43) + (#38) - (#24+ #30+ #34)

(2.4 + 2.3 + 3.6) + (5.0) - (2.4 + 2.3 + 4.1)

4.5 ns

=

=

=

=

Clock (max) + Reg co + Output

(

(#24 + #30 + #43) + (#39) + (#44 + #46)

(2.4 + 2.3 + 3.6) + (1.6) + (1.2 + 2.6)

13.7 ns

Table 2- 0042-3256E