ISPPACCLK5304S-01T48C datasheet(5/56 Pages) LATTICE

Part #	ISPPACCLK5304S-01T48C

Description	In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended

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Manufacturer	LATTICE [Lattice Semiconductor]

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Lattice Semiconductor

ispClock5300S Family Data Sheet

5

Absolute Maximum Ratings

ispClock5300S

Core Supply Voltage VCCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V

PLL Supply Voltage VCCA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V

JTAG Supply Voltage VCCJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V

Output Driver Supply Voltage VCCO . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V

Output Voltage

1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C

Junction Temperature with power supplied . . . . . . . . . . . . . . . . . . . -40 to 130°C

1. When applied to an output when in high-Z condition

Recommended Operating Conditions

Recommended Operating Conditions – VCCO vs. Logic Standard

Symbol

Parameter

Conditions

ispClock5300S

Units

Min.

Max.

VCCD

Core Supply Voltage

3.0

3.6

V

VCCJ

JTAG I/O Supply Voltage

1.62

3.6

V

VCCA

Analog Supply Voltage

3.0

3.6

V

VCCXSLEW

VCC Turn-on Ramp Rate

All supply pins

—

0.33

V/µs

TJOP

Operating Junction Temperature

Commercial

0

120

°C

Industrial

-40

130

TA

Ambient Operating Temperature

Commercial

0

70

1

°C

Industrial

-40

85

1

1. Device power dissipation may also limit maximum ambient operating temperature.

VCCO (V)

VREF (V)

VTT (V)

Logic Standard

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Typ.

Max.

LVTTL

3.0

3.3

3.6

—

LVCMOS 1.8V

1.71

1.8

1.89

—

LVCMOS 2.5V

2.375

2.5

2.625

—

LVCMOS 3.3V

3.0

3.3

3.6

—

SSTL1.8

1.71

1.8

1.89

0.84

0.90

0.95

—

0.5 x VCCO

—

SSTL2 Class 1

2.375

2.5

2.625

1.15

1.25

1.35

VREF - 0.04

VREF

VREF + 0.04

SSTL3 Class 1

3.0

3.3

3.6

1.30

1.50

1.70

VREF - 0.05

VREF

VREF + 0.05

HSTL Class 1

1.425

1.5

1.575

0.68

0.75

0.90

—

0.5 x VCCO

—

eHSTL Class 1

1.71

1.8

1.89

0.84

0.90

0.95

—

0.5 x VCCO

—

Note: ‘—’ denotes VREF or VTT not applicable to this logic standard

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