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ISPPACCLK5520V-01T100C Datasheet(PDF) 1 Page - Lattice Semiconductor

Part # ISPPACCLK5520V-01T100C
Description  In-System Programmable Clock Generator with Universal Fan-Out Buffer
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

ISPPACCLK5520V-01T100C Datasheet(HTML) 1 Page - Lattice Semiconductor

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www.latticesemi.com
1
clk5500_06.2
March 2005
Data Sheet
© 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
ispClock 5500 Family
In-System Programmable Clock Generator
with Universal Fan-Out Buffer
Features
■ 10MHz to 320MHz Input/Output Operation
■ Low Output to Output Skew (<50ps)
■ Low Jitter Peak-to-Peak(<70ps)
■ Up to 20 Programmable Fan-out Buffers
• Programmable output standards and individual
enable controls
- LVTTL, LVCMOS, HSTL, SSTL, LVDS,
LVPECL
• Programmable output impedance
- 40 to 70Ω in 5Ω increments
• Programmable slew rate
• Up to 10 banks with individual VCCO and GND
- 1.5V, 1.8V, 2.5V, 3.3V
■ Fully Integrated High-Performance PLL
• Programmable lock detect
• Multiply and divide ratio controlled by
- Input divider (5 bits)
- Internal feedback divider (5 bits)
- Five output dividers (5 bits)
• Programmable On-chip Loop Filter
■ Precision Programmable Phase Adjustment
(Skew) Per Output
• 16 settings; minimum step size 195ps
- Locked to VCO frequency
• Up to +/- 12ns skew range
• Coarse and fine adjustment modes
■ Up to Five Clock Frequency Domains
■ Flexible Clock Reference Inputs
• Programmable input standards
- LVTTL, LVCMOS, SSTL, HSTL, LVDS,
LVPECL
• Clock A/B selection multiplexer
• Programmable precision termination
■ Four User-programmable Profiles Stored in
E
2CMOS® Memory
• Supports both test and multiple operating
configurations
■ Full JTAG Boundary Scan Test In-System
Programming Support
■ Exceptional Power Supply Noise Immunity
■ Commercial (0 to 70°C) and Industrial
(-40 to 85°C) Temperature Ranges
■ 100-pin and 48-pin TQFP Packages
■ Applications
• Circuit board common clock generation and
distribution
• PLL-based frequency generation
• High fan-out clock buffer
Product Family Block Diagram
VCO
OUTPUT
DRIVERS
SKEW
CONTROL
M
N
JTAG
INTERFACE
&
E2CMOS
MEMORY
LOCK DETECT
FILTER
PHASE/
FREQUENCY
DETECTOR
1
02
3
Multiple Profile
Management Logic
INTERNAL FEEDBACK PATH
PLL CORE
OUTPUT
ROUTING
MATRIX
V0
V1
V2
V3
V4
OUTPUT
DIVIDERS
*
* Input Available only on ispClock 5520
BYPASS
MUX


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