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ISPPACCLK5510V-01T48C Datasheet(PDF) 2 Page - Lattice Semiconductor |
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ISPPACCLK5510V-01T48C Datasheet(HTML) 2 Page - Lattice Semiconductor |
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2 / 48 page  Lattice Semiconductor ispClock5500 Family Data Sheet 2 General Description and Overview The ispClock5510 and ispClock5520 are in-system-programmable high-fanout PLL-based clock drivers designed for use in high performance communications and computing applications. The ispClock5510 provides up to 10 sin- gle-ended or five differential clock outputs, while the ispClock5520 provides up to 20 single-ended or 10 differential clock outputs. Each pair of outputs may be independently configured to support separate I/O standards (LVDS, LVPECL, LVTTL, LVCMOS, SSTL, HSTL) and output frequency. In addition, each output provides independent pro- grammable control of termination, slew-rate, and timing skew. All configuration information is stored on-chip in non- volatile E 2CMOS memory. The ispClock5500’s PLL and divider systems supports the synthesis of clock frequencies differing from that of the reference input through the provision of programmable input and feedback dividers. A set of five post-PLL V-divid- ers provides additional flexibility by supporting the generation of five separate output frequencies. Loop feedback may be taken from the output of any of the five V-dividers. The core functions of all members of the ispClock5500 family are identical, the differences between devices being restricted to the number of inputs and outputs, as shown in the following table. Figures 1 and 2 show functional block diagrams of the ispClock5510 and ispClock5520. Table 1. ispClock5500 Family Members Figure 1. ispClock5510 Functional Block Diagram Device Ref. Input Pairs Clock Outputs ispClock5510 1 10 ispClock5520 2 20 VCO LOOP FILTER PHASE DETECT LOCK DETECT M N INPUT DIVIDER FEEDBACK SKEW ADJUST 1 0 FEEDBACK DIVIDER GOE OEX LOCK PLL_BYPASS JTAG INTERFACE OEY TDI TMS TCK TDO SGATE SKEW CONTROL OUTPUT DRIVERS BANK_3A BANK_3B BANK_4A BANK_4B OUTPUT DIVIDERS OUTPUT ROUTING MATRIX RESET V1 V2 V0 V3 V4 BANK_0A BANK_0B BANK_1A BANK_1B BANK_2A BANK_2B PS0 PS1 Profile Select Control 0123 OUTPUT ENABLE CONTROLS (1-32) (1-32) (2-64) (2-64) (2-64) (2-64) (2-64) REFA+ REFA- REFVTT |
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