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ISPPACCLK5510V-01TN100I Datasheet(PDF) 8 Page - Lattice Semiconductor

Part # ISPPACCLK5510V-01TN100I
Description  In-System Programmable Clock Generator with Universal Fan-Out Buffer
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

ISPPACCLK5510V-01TN100I Datasheet(HTML) 8 Page - Lattice Semiconductor

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Lattice Semiconductor
ispClock5500 Family Data Sheet
8
Output Test Loads
Figures 3-5 show the equivalent termination loads used to measure rise/fall times, output timing adders and other
selected parameters as noted in the various tables of this data sheet.
Figure 3. CMOS Termination Load
Figure 4. HSTL/SSTL Termination Load
Figure 5. LVDS/LVPECL Termination Load
ispCLOCK
SCOPE
950Ω
50Ω/3"
50Ω/36"
50Ω 5pF
Zo = 50Ω
ispCLOCK
SCOPE
50Ω/3"
50Ω/36"
950Ω
50Ω 5pF
Zo = HSTL: ~20Ω
SSTL: 40Ω
VTERM
50Ω
ispCLOCK
50Ω/36"
34Ω
34Ω
50Ω/36"
0.1U
0.1U
44.2Ω
3pF
(parasitic)
3pF
(parasitic)
SCOPE
50Ω
50Ω
5pF
5pF
ChA
ChB
50Ω/3"
50Ω/1"
50Ω/3"
50Ω/1"
Interface Circuit
33.2Ω
33.2Ω


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