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ISPPACCLK5312S-01T64I Datasheet(PDF) 2 Page - Lattice Semiconductor |
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ISPPACCLK5312S-01T64I Datasheet(HTML) 2 Page - Lattice Semiconductor |
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2 / 56 page  Lattice Semiconductor ispClock5300S Family Data Sheet 2 General Description The ispClock5300S is an in-system-programmable zero delay universal fan-out buffer for use in clock distribution applications. The ispClock5312S, the first member of the ispClock5300S family, provides up to 12 single-ended ultra low skew outputs. Each pair of outputs may be independently configured to support separate I/O standards (LVTTL, LVCMOS -3.3V, 2.5V, 1.8, SSTL, HSTL) and output frequency. In addition, each output provides indepen- dent programmable control of termination, slew-rate, and timing skew. All configuration information is stored on- chip in non-volatile E 2CMOS® memory. The ispClock5300S devices provide extremely low propagation delay (zero-delay) from input to output using the on-chip low jitter high-performance PLL. A set of three programmable 5-bit counters can be used to generate three frequencies derived from the PLL clock. These counters are programmable in powers of 2 only (1, 2, 4, 8, 16, 32). The clock output from any of the V-dividers can then be routed to any clock output pin through the output routing matrix. The output routing matrix, in addition, also enables routing of reference clock inputs directly to any output. The ispClock5300S device can be configured to operate in four modes: zero delay buffer mode, dual non-zero delay buffer mode, non-zero delay buffer mode with output dividers, and combined zero-delay and non-zero delay buffer mode. The core functions of all members of the ispClock5300S family are identical. Table 1 summarizes the ispClock5300S device family. Table 1. ispClock5300S Family Figure 1. ispClock5304S Functional Block Diagram Device Number of Programmable Clock Inputs Number of Programmable Single-Ended Outputs ispClock5320S 1 Differential, 2 Single-Ended 20 ispClock5316S 1 Differential, 2 Single-Ended 16 ispClock5312S 1 Differential, 2 Single-Ended 12 ispClock5308S 1 Differential, 2 Single-Ended 8 ispClock5304S 1 Differential, 2 Single-Ended 4 + VCO LOOP FILTER PHASE DETECT LOCK DETECT REFA_REFP REFSEL VTT_REFB 1 0 OEX S S A P Y B _ L L P K C O L JTAG INTERFACE OEY TDO TCK TMS TDI SKEW CONTROL OUTPUT DRIVERS SKEW CONTROL OUTPUT DRIVERS OUTPUT DIVIDERS OUTPUT ROUTING MATRIX RESET V1 V2 V0 BANK_0A BANK_0B BANK_1A BANK_1B OUTPUT ENABLE CONTROLS 5-bit 5-bit 5-bit 0 1 FBK REFB_REFN VTT_REFA VTT_FBK |
Similar Part No. - ISPPACCLK5312S-01T64I |
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Similar Description - ISPPACCLK5312S-01T64I |
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