ISPCLOCK5520 datasheet(7/48 Pages) LATTICE

Part #	ISPCLOCK5520

Description	In-System Programmable Clock Generator with Universal Fan-Out Buffer

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Manufacturer	LATTICE [Lattice Semiconductor]

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Lattice Semiconductor

ispClock5500 Family Data Sheet

7

Switching Characteristics – Timing Adders for I/O Modes

Output Rise and Fall Times – Typical Values

1, 2

Adder Type

Base Parameter(s)

Description

Min.

Typ.

Max.

Units

tIOI Input Adders

2

LVTTL_in

Using LVTTL Standard

—

0

—

ns

LVCMOS18_in

Using LVCMOS 1.8V Standard

—

0

—

ns

LVCMOS25_in

Using LVCMOS 2.5V Standard

—

0

—

ns

LVCMOS33_in

Using LVCMOS 3.3V Standard

—

0

—

ns

SSTL2_in

Using SSTL2 Standard

—

0.4

—

ns

SSTL3_in

Using SSTL3 Standard

—

0.4

—

ns

HSTL_in

Using HSTL Standard

—

0.4

—

ns

LVDS_in

Using LVDS Standard

—

1.8

—

ns

LVPECL_in

Using LVPECL Standard

—

1.8

—

ns

tIOO Output Adders

1, 3

LVTTL_out

Output Conﬁgured as LVTTL Buffer

—

0.1

—

ns

LVCMOS18_out

Output Conﬁgured as LVCMOS 1.8V Buffer

—

0.1

—

ns

LVCMOS25_out

Output Conﬁgured as LVCMOS 2.5V Buffer

—

0.1

—

ns

LVCMOS33_out

Output Conﬁgured as LVCMOS 3.3V Buffer

—

0.1

—

ns

SSTL2_out

Output Conﬁgured as SSTL2 Buffer

—

0.1

—

ns

SSTL3_out

Output Conﬁgured as SSTL3 Buffer

—

0.1

—

ns

HSTL_out

Output Conﬁgured as HSTL Buffer

—

0.1

—

ns

LVDS_out

Output Conﬁgured as LVDS Buffer

—

0.1

—

ns

LVPECL_out

Output Conﬁgured as LVPECL Buffer

—

0

—

ns

tIOS Output Slew Rate Adders

1

Slew_1

Output Slew_1 (Fastest)

—

0

—

ps

Slew_2

Output Slew_2

—

330

—

ps

Slew_3

Output Slew_3

—

660

—

ps

Slew_4

Output Slew_4 (Slowest)

—

1320

—

ps

1. Measured under standard output load conditions – see Figures 3-5.

2. All input adders referenced to LVTTL.

3. All output adders referenced to LVPECL.

Output Type

Slew 1 (Fastest)

Slew 2

Slew 3

Slew 4 (Slowest)

Units

tR

tF

tR

tF

tR

tF

tR

tF

LVTTL

0.65

0.45

0.85

0.60

1.20

0.90

1.75

1.30

ns

LVCMOS 1.8V

0.90

0.40

1.05

0.50

1.40

0.80

2.00

1.20

ns

LVCMOS 2.5V

0.70

0.40

0.90

0.55

1.20

0.85

1.80

1.20

ns

LVCMOS 3.3V

0.65

0.45

0.85

0.60

1.20

0.90

1.75

1.30

ns

SSTL2

0.65

0.40

0.90

0.60

1.35

0.85

2.30

1.40

ns

SSTL3

0.65

0.40

0.90

0.60

1.35

0.85

2.30

1.40

ns

HSTL

0.85

0.30

1.00

0.50

1.50

0.70

2.55

1.10

ns

LVDS

3

0.25

0.20

——————

ns

LVPECL

3

0.20

——————

ns

1. See Figures 3-5 for test conditions.

2. Measured between 20% and 80% points.

3. Only the ‘fastest’ slew rate is available in LVDS and LVPECL modes.

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