AC Test Conditions

Input Pulse Level

0.6V to 2.0V

Input Rise and Fall Time

5ns

Input and Output Timing

Reference Level

50% of input level

Output Load Condition

70ns/85 ns

C

Load 100ns/150 ns

C

C

Figure A.

* Including Scope and Jig Capacitance

TTL

V62C2801024L(L)

Input Leakage Current

-

1

-

1

-

1

-

1

µA

Output Leakage

Current

LO

-

1

-

1

-

1

-

1

µA

Operating Power

Supply Current

-

3

-

3

-

3

-

3

mA

Average Operating

Current

Min Cycle, 100% Duty

-

25

-

20

-

15

-

15

mA

Cycle Time=1

µs, 100% Duty

-

3

-

3

-

3

-

3

mA

Standby Power Supply

Current (TTL Level)

-

0.5

-

0.5

-

0.5

-

0.5

mA

Standby Power Supply

Current (CMOS Level)

L

CE2 < 0.2V, f = 0

LL

-

-

5

1

-

-

5

1

-

-

5

1

-

-

5

1

µA

µA

Output Low Voltage

-

0.4

-

0.4

-

0.4

-

0.4

V

Output High Voltage

2.0

-

2.0

-

2.0

-

2.0

-

V

-70

-100

-150

Unit

Parameter

Sym

Test Conditions

Min Max Min Max Min Max Min Max

-85

4

Parameter*

Symbol

Test Condition

Max

Unit

Input Capacitance

7

pF

I/O Capacitance

8

pF

* This parameter is guaranteed by device characterization and is not production tested.

REV. 1.1 April 2001 V62C2801024L(L)