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V62C2802048L-85T Datasheet(PDF) 1 Page - Mosel Vitelic, Corp |
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V62C2802048L-85T Datasheet(HTML) 1 Page - Mosel Vitelic, Corp |
1 / 10 page V62C2802048L(L) Ultra Low Power 256K x 8 CMOS SRAM Features • Low-power consumption - Active: 35mA at 55ns - Stand-by: 10 µA (CMOS input/output) 2 µA CMOS input/output, L version • Single +2.2 to 2.7V Power Supply_Typical • Extented Voltage from 2.2 to 3.6V. • Equal access and cycle time • 55/70/85/100 ns access time • Easy memory expansion with CE1, CE2 and OE inputs • 1.0V data retention mode • TTL compatible, Tri-state input/output • Automatic power-down when deselected • Package available: 32L TSOP(I)/ STSOP(I) • 48 Ball CSP_BGA Functional Description The V62C2802048L is a low power CMOS Static RAM organized as 262,144 words by 8 bits. Easy memory exp- ansion is provided by an active LOW CE1, an active HIGH CE2, an active LOW OE, and Tri-state I/O’s. This device has an automatic power-down mode feature when deselected. Writing to the device is accomplished by taking Chip Enable 1 (CE1) with Write Enable (WE) LOW, and Chip Enable 2 (CE2) HIGH. Reading from the device is per- formed by taking Chip Enable 1 (CE1) with Output Enable (OE) LOW while Write Enable (WE) and Chip Enable 2 (CE2) is HIGH. The I/O pins are placed in a high-impedance state when the device is deselected: the outputs are disabled during a write cycle. TheV62C2802048LL comes with a 1V data retention fe- ature and Lower Standby Power. The V62C2802048L is avalable in a 32-pin 8 x 20 mm TSOP1 / STSOP 8x13.4 mm and CSP type 48-fpBGA packages. 32-Pin TSOP1 / STSOP (CSP_BGA See next page) Logic Block Diagram Cell Array INPUT BUFFER COLUMN DECODER CONTROL CIRCUIT I/O8 I/O1 OE WE CE1 CE2 A8 A7 A6 A5 A4 A3 A2 A1 A0 A9 A10 A11 A12 A13 A14 A15 A16 A17 1 2 3 4 5 6 7 8 9 16 15 14 13 12 11 10 A8 A9 A11 A13 WE CE2 A15 Vcc A17 A16 A14 A12 A7 A6 A5 A4 32 31 30 29 28 27 26 25 24 17 18 19 20 21 22 23 CE1 A10 OE I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3 REV. 1.2 May 2001 V62C2802048L(L) 1 |
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