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M48Z58-70MH1E Datasheet(PDF) 9 Page - STMicroelectronics |
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M48Z58-70MH1E Datasheet(HTML) 9 Page - STMicroelectronics |
9 / 23 page M48Z58, M48Z58Y Operating modes 9/23 Figure 5. Read mode AC waveforms Note: WRITE Enable (W) = High. Table 3. Read mode AC characteristics 2.2 Write mode The M48Z58/Y is in the WRITE Mode whenever W and E are low. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls. Symbol Parameter(1) 1. Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). M48Z58/Y Unit Min Max tAVAV READ cycle time 70 ns tAVQV Address valid to output valid 70 ns tELQV Chip enable low to output valid 70 ns tGLQV Output enable low to output valid 35 ns tELQX (2) 2. CL = 5pF (see Figure 9 on page 14). Chip enable low to output transition 5 ns tGLQX (2) Output enable low to output transition 5 ns tEHQZ (2) Chip enable high to output Hi-Z 25 ns tGHQZ (2) Output enable high to output Hi-Z 25 ns tAXQX Address transition to output transition 10 ns AI01385 tAVAV tAVQV tAXQX tELQV tELQX tEHQZ tGLQV tGLQX tGHQZ VALID A0-A12 E G DQ0-DQ7 VALID |
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