M48Z32V

Operating modes

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2

Operating modes

The M48Z32V also has its own Power-fail Detect circuit. The control circuitry constantly

tolerance, the circuit write protects the SRAM, providing a high degree of data security in the

power returns.

Table 2.

Operating modes

Note:

2.1

Read mode

The M48Z32V is in the READ Mode whenever W (WRITE Enable) is high, E (Chip Enable)

is low. The device architecture allows ripple-through access of data from eight of 262,144

locations in the static storage array. Thus, the unique address specified by the 15 Address

Inputs defines which one of the 32,768 bytes of data is to be accessed. Valid data will be

signal is stable, providing that the E and G access times are also satisfied. If the E and G

access times are not met, valid data will be available after the latter of the Chip Enable

The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are

the Address Inputs are changed while E and G remain active, output data will remain valid

Mode

E

G

W

DQ0-DQ7

Power

Deselect

3.0 to 3.6V

X

X

High Z

Standby

WRITE

Active

READ

Active

READ

High Z

Active

Deselect

(1)

1.

See Table 12 on page 15 for details.

X

X

X

High Z

CMOS standby

Deselect

≤ VSO(1)

X

X

X

High Z

Battery back-up

mode