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M48T58-70PC1E Datasheet(PDF) 9 Page - STMicroelectronics |
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M48T58-70PC1E Datasheet(HTML) 9 Page - STMicroelectronics |
9 / 31 page M48T58, M48T58Y Read mode 9/31 3 Read mode The M48T58/Y is in the READ Mode whenever W (WRITE Enable) is high, E1 (Chip Enable 1) is low, and E2 (Chip Enable 2) is high. The unique address specified by the 13 Address Inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E1, E2, and G access times are also satisfied. If the E1, E2 and G access times are not met, valid data will be available after the latter of the Chip Enable Access times (tE1LQV or tE2HQV) or Output Enable Access time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E1, E2 and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E1, E2 and G remain active, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access. Figure 5. Read mode AC waveforms Note: WRITE Enable (W) = High. AI00962 tAVAV tAVQV tAXQX tE1LQV tE1LQX tE1HQZ tGLQV tGLQX tGHQZ VALID A0-A12 E1 G DQ0-DQ7 tE2HQV tE2HQX VALID tE2LQZ E2 |
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