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USBLC6-4 Datasheet(PDF) 5 Page - STMicroelectronics |
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USBLC6-4 Datasheet(HTML) 5 Page - STMicroelectronics |
5 / 13 page USBLC6-4 Technical information 5/13 Figure 6. ESD behavior: parasitic phenomena due to unsuitable layout 2.3 How to ensure good ESD protection While the USBLC6-4SC6 provides high immunity to ESD surge, efficient protection depends on the layout of the board. In the same way, with the rail to rail topology, the track from data lines to I/O pins, from VCC to the VBUS pin and from GND plane to GND pin must be as short as possible to avoid overvoltages due to parasitic phenomena (see Figure 7 and Figure 8 for layout considerations) VBUS LI/O LVBUS LGND LI/O LGND V pin CC VCL VF I/O pin VTRANSIL V+ V TRANSIL F -VF VCL- t = 1 ns r t t t = 1 ns r VCL+ GND pin Data line Positive Sur ge Negative Sur ge ESD sur ge on data line di dt LI/O + LGND di dt di dt -LI/O - LGND di dt di dt V + =V +V + L + L sur ge > 0 CL TRANSIL F I/O GND V = -V - L - L sur ge > 0 CL- F I/O GND di dt di dt di dt di dt di dt Rd.Ip V V BR TRANSIL + = Figure 7. ESD behavior: optimized layout and addition of a capacitance of 100 nF Figure 8. ESD behavior: measurement conditions (with coupling capacitance) Unsuitable layout Optimized layout TEST BOARD Vbus ESD SURGE OUT IN USBLC6-4SC6 |
Similar Part No. - USBLC6-4_08 |
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Similar Description - USBLC6-4_08 |
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