74LVQ573TTR datasheet(1/13 Pages) STMICROELECTRONICS

Part #	74LVQ573TTR

Description	LOW VOLTAGE CMOS OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING

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July 2004

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HIGH SPEED:

tPD = 5.8 ns (TYP.) at VCC = 3.3 V

s

COMPATIBLE WITH TTL OUTPUTS

s

LOW POWER DISSIPATION:

ICC = 4 µA (MAX.) at TA=25°C

s

LOW NOISE:

VOLP = 0.5V (TYP.) at VCC = 3.3V

s

75

Ω TRANSMISSION LINE DRIVING

CAPABILITY

s

SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 12mA (MIN) at VCC = 3.0 V

s

PCI BUS LEVELS GUARANTEED AT 24 mA

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BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s

OPERATING VOLTAGE RANGE:

VCC(OPR) = 2V to 3.6V (1.2V Data Retention)

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PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 573

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IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74LVQ573 is a low voltage CMOS OCTAL

D-TYPE LATCH with 3 STATE OUTPUTS NON

INVERTING fabricated with sub-micron silicon

gate and double-layer metal wiring C2MOS

technology. It is ideal for low power and low noise

3.3V applications.

These 8 bit D-Type latch are controlled by a latch

enable input (LE) and an output enable input (OE).

While the LE input is held at a high level, the Q

outputs will follow the data input precisely.

When the LE is taken low, the Q outputs will be

latched precisely at the logic level of D input data.

While the (OE) input is low, the 8 outputs will be in

a normal logic state (high or low logic level) and

while high level the outputs will be in a high

impedance state. In order to enhance PC board

layout, the 74LVQ573 offers a pinout having inputs

and outputs on opposite side of the package.

All

inputs

and

outputs

are

equipped

with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

74LVQ573

LOW VOLTAGE CMOS OCTAL D-TYPE LATCH

WITH 3 STATE OUTPUTS NON INVERTING

Figure 1: Pin Connection And IEC Logic Symbols

Table 1: Order Codes

PACKAGE

T & R

SOP

74LVQ573MTR

TSSOP

74LVQ573TTR

TSSOP

SOP

Rev. 5

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74LVQ573TTR Datasheet(PDF) 1 Page - STMicroelectronics

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