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74LVQ74TTR Datasheet(PDF) 1 Page - STMicroelectronics |
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74LVQ74TTR Datasheet(HTML) 1 Page - STMicroelectronics |
1 / 13 page 1/13 July 2004 s HIGH SPEED: fMAX = 250 MHz (TYP.) at VCC = 3.3V s COMPATIBLE WITH TTL OUTPUTS s LOW POWER DISSIPATION: ICC =2 µA (MAX.) at TA=25°C s LOW NOISE: VOLP = 0.2 V (TYP.) at VCC = 3.3V s 75 Ω TRANSMISSION LINE DRIVING CAPABILITY s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12mA (MIN) at VCC = 3.0V s PCI BUS LEVELS GUARANTEED AT 24 mA s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74 s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74LVQ74 is a low voltage CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. A signal on the D INPUT is transferred to the Q OUTPUT during the positive going transition of the clock pulse. CLEAR and PRESET are independent of the clock and accomplished by a low setting on the appropriate input. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74LVQ74 DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR Figure 1: Pin Connection And IEC Logic Symbols Table 1: Order Codes PACKAGE T & R SOP 74LVQ74MTR TSSOP 74LVQ74TTR TSSOP SOP Rev. 5 |
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