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STLC5444B1 Datasheet(PDF) 9 Page - STMicroelectronics |
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STLC5444B1 Datasheet(HTML) 9 Page - STMicroelectronics |
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9 / 17 page  OPERATIVE DESCRIPTION. Initialization The device is initialized by the RESET pin. In this state the analog drivers are switched off, the Indi- rect Address Register (IAR) is cleared, and the in- ternally latched address A0 is cleared. Power at Output drivers The voltage at the Output drivers is approximately VBB (more precisely: VBB -VSAT). Analog Section The analog section consists of four line drivers, which are DMOS transistor switches capable of sinking up to 120 mA each. The power to the driv- ers is derived from the negative supply voltage (VBB). The output voltage to each line is slaved to VBB, and the voltage drop in each driver is ap- proximately 1.5V. Line driver protection is provided through the inte- gration of current limit and over-temperature shut- off. The current limit is hardware-programmable via an external resistor (RLIM) connected be- tween ILIM and VBB. The output limit is : 5mA + 1000 x 1.25V/RLIM. This 1000 x gain makes the ILIM pin susceptible to external noise, care should be taken to connect RLIM as close as possible to the component. The thermal shut-off is internally set at approxi- mately 160 oC. At this temperature all the drivers are uncondition- ally switched off. However, at approximately 130 oC, only the drivers that are in the current- overload condition will be turned off. Status detectors, associated with each of the line drivers, monitor the load conditions on each line by comparing an electrical parameter (e.g., cur- rent and voltage at the line) with reference level. The output of each detector can be read by the microprocessor. In addition to these status detec- tors, the temperature of the device is monitored via integrated temperature detectors. The detec- tors respond at approximately 130 oC and 160oC, as defined above, and the 160 oC detector can be monitored by the microprocessor via the MPI. The status detectors provide the following information from each of the lines (all detectors have built-in hysteresis) : *) Low Output Voltage Detection The low-output-voltage status bit becomes ac- tive when the voltage across the output DMOS transistor exceeds the proper voltage threshold (VLVD). *) Open Loop Detection The open-loop status bit becomes active when the current on the line drops below a minimum value. *) Current Overload Detection The current-overload status bits become active when the current on the line nears the current limit. These bits active the INT output if COD in- terrupts are enabled via the IAR Register. *) Thermal Overload Detection If the device temperature reaches 130 oC, then all the line drivers in the current-overload condi- tion will be switched off and the corresponding bits in the Thermal Overload Register will be activated. If the device temperature increases to 160 oC, all the line drivers will be turned off, and all the bits in the Thermal Overload Regis- ter will be activated. The T-bit will also be set, and it can be read along with the Indirect Address Register (IAR) to indicate that all the drivers have been turned off. To initialize any of the bits in the Thermal Overload Register, the microprocessor must first turn off the line drivers that must not be re- activated until the T-bit in the address register is cleared by the temperature detector in the device. MPI Section The MPI allows the user to access the detectors defined in the analog section. The line driver’s status bits are grouped by function. Bits 3-0 of the detectors correspond to lines 3-0, respectively. The status group are : Low Voltage Detector (LVD) Open Loop Detector (OLD) Current Overload Detector (COD) Thermal Overload Register (TOR) The data is not latched in these status groups ex- cept in the TOR. Thus, the user should filter (multiple samples) the received data to ensure its integrity. There are two other registers in the MPI: the Indirect Ad- dress Register (IAR), and Line Enable Register (LER). The IAR contains 3 bits that address the desired status group or the LER. The IAR is read along with the T-bit defined in the analog section. The microprocessor can read the IAR to check the va- lidity of the address. A 1us delay is required be- tween a write to the LER register, followed by a Read of the same register. Subsequent reads of the LER do not have this constraint. STLC5444 9/17 |
Similar Part No. - STLC5444B1 |
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Similar Description - STLC5444B1 |
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