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STLC3055QTR Datasheet(PDF) 8 Page - STMicroelectronics |
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STLC3055QTR Datasheet(HTML) 8 Page - STMicroelectronics |
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8 / 22 page  obtained with a 20Hz and 25Hz ring frequency and with 1REN. This value are valid either with European or USA specification: CREV CREST FACTOR @20Hz CREST FACTOR @25Hz 22nF 1.2 1.26 27nF 1.25 1.32 33nF 1.33 Not significant (*) (*) Distorsion already less than 10%. The ring trip detection is performed sensing the variation of the AC line impedance from on hook (relatively high) to off-hook (low). This particular ring trip method allows to operate without DC off- set superimposed on the ring signal and therefore obtaining the maximum possible ring level on the load starting from a given negative battery. It should be noted that such a method is opti- mised for operation on short loop applications and may not operate properly in presence of long loop applications (> 500 Ω ). Once ring trip is detected, the DET output is acti- vated (logic level low), at this point the card con- troller or a simple logic circuit should stop the D2 toggling in order to effectively disconnect the ring signal and then set the STLC3055 in the proper operating mode (normally ACTIVE). RING LEVEL IN PRESENCE OF MORE TELE- PHONE IN PARALLEL As already mentioned above the maximum cur- rent that can be drawn from the Vpos supply is controlled and limited via the external RSENSE. This will limit also the power available at the self generated negative battery. If for any reason the ringer load will be too high the self generated battery will drop in order to keep the power consumption to the fixed limit and therefore also the ring voltage level will be re- duced. In the typical application with RSENSE = 110m Ω the peak current from Vpos is limited to about 900mA, which correspond to an average current of 700mA max. In this condition the STLC3055 can drive up to 3REN with a ring frequency fr=25Hz (1REN = 1800 Ω + 1.0µF, European standard). In order to drive up to 5REN (1REN= 6930 Ω + 8 µF, US standard) it is necessary to modify the external components as follows: CREV = 15nF RD = 2.2K Ω Power On Requirements In order to avoid damage to the device when Vpos is first applied it is recommended to keep all the logic inputs to a low logic level (0V) until Vpos is >5.5V. In case this power up sequence cannot be guar- anteed it’s recommended to connect a shottky di- ode (BAT46 or equivalent) between VBAT and BGND see figure below. GND TIP RING dV/dT set by CREV 2.5V typ. 65V typ. VBAT 2.5V typ. Figure 5. TIP/RING typical ringing waveform BAT46 BGND VBAT STLC3055 Figure 6. Shottky diode connection STLC3055 8/22 |
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