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MC74HCXXXADT Datasheet(PDF) 1 Page - Motorola, Inc |
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MC74HCXXXADT Datasheet(HTML) 1 Page - Motorola, Inc |
1 / 9 page MOTOROLA SEMICONDUCTOR TECHNICAL DATA 1 REV 0 © Motorola, Inc. 1995 10/95 Product Preview 8-Bit Serial or Parallel-Input/ Serial-Output Shift Register High–Performance Silicon–Gate CMOS The MC54/74HC165A is identical in pinout to the LS165. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device is an 8–bit shift register with complementary outputs from the last stage. Data may be loaded into the register either in parallel or in serial form. When the Serial Shift/Parallel Load input is low, the data is loaded asynchronously in parallel. When the Serial Shift/Parallel Load input is high, the data is loaded serially on the rising edge of either Clock or Clock Inhibit (see the Function Table). The 2–input NOR clock may be used either by combining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit. • Output Drive Capability: 10 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2 to 6 V • Low Input Current: 1 µA • High Noise Immunity Characteristic of CMOS Devices • In Compliance with the Requirements Defined by JEDEC Standard No. 7A • Chip Complexity: 286 FETs or 71.5 Equivalent Gates FUNCTION TABLE Inputs Internal Stages Output Operation Serial Shift/ Parallel Load Clock Clock Inhibit SA A – H QA QB QH Operation L X X X a … h a b h Asynchronous Parallel Load H H L L L H X X L H QAn QAn QGn QGn Serial Shift via Clock H H L L L H X X L H QAn QAn QGn QGn Serial Shift via Clock Inhibit H H X H H X X X X X No Change Inhibited Clock H L L X X No Change No Clock X = don’t care QAn – QGn = Data shifted from the preceding stage This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. MC54/74HC165A PIN ASSIGNMENT 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 B C D CLOCK INHIBIT VCC QH SA A F E CLOCK SERIAL SHIFT/ PARALLEL LOAD GND QH H G D SUFFIX SOIC PACKAGE CASE 751B–05 N SUFFIX PLASTIC PACKAGE CASE 648–08 ORDERING INFORMATION MC54HCXXXAJ MC74HCXXXAN MC74HCXXXAD MC74HCXXXADT Ceramic Plastic SOIC TSSOP 1 16 1 16 J SUFFIX CERAMIC PACKAGE CASE 620–10 1 16 1 16 DT SUFFIX TSSOP PACKAGE CASE 948F–01 LOGIC DIAGRAM PIN 16 = VCC PIN 8 = GND 11 12 13 14 3 4 5 6 10 A B C D E F G H SA PARALLEL DATA INPUTS SERIAL DATA INPUT SERIAL SHIFT/ PARALLEL LOAD 1 2 15 CLOCK CLOCK INHIBIT 9 7 QH QH SERIAL DATA OUTPUTS |
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