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MC74HC174AD Datasheet(PDF) 1 Page - Motorola, Inc |
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MC74HC174AD Datasheet(HTML) 1 Page - Motorola, Inc |
1 / 6 page MOTOROLA SEMICONDUCTOR TECHNICAL DATA 1 REV 6 © Motorola, Inc. 1995 10/95 Hex D Flip-Flop with Common Clock and Reset High–Performance Silicon–Gate CMOS The MC54/74HC174A is identical in pinout to the LS174. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of six D flip–flops with common Clock and Reset inputs. Each flip–flop is loaded with a low–to–high transition of the Clock input. Reset is asynchronous and active–low. • Output Drive Capability: 10 LSTTL Loads • TTL NMOS Compatible Input Levels • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 4.5 to 5.5 V • Low Input Current: 1.0 µA • In Compliance with the Requirements Defined by JEDEC Standard No. 7A • Chip Complexity: 162 FETs or 40.5 Equivalent Gates LOGIC DIAGRAM PIN 16 = VCC PIN 8 = GND 3 4 6 11 13 14 2 5 7 10 12 15 D0 D1 D2 D3 D4 D5 Q0 Q1 Q2 Q3 Q4 Q5 CLOCK 9 RESET 1 DATA INPUTS NONINVERTING OUTPUTS Design Criteria Value Units Internal Gate Count* 40.5 ea. Internal Gate Propagation Delay 1.5 ns Internal Gate Power Dissipation 5.0 µW Speed Power Product .0075 pJ * Equivalent to a two–input NAND gate. MC54/74HC174A PIN ASSIGNMENT FUNCTION TABLE Inputs Output Reset Clock D Q L X X L H H H H L L H L X No Change H X No Change 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 Q4 D4 D5 Q5 VCC CLOCK Q3 D3 D1 D0 Q0 RESET GND Q2 D2 Q1 D SUFFIX SOIC PACKAGE CASE 751B–05 N SUFFIX PLASTIC PACKAGE CASE 648–08 ORDERING INFORMATION MC54HCXXXAJ MC74HCXXXAN MC74HCXXXAD Ceramic Plastic SOIC 1 16 1 16 J SUFFIX CERAMIC PACKAGE CASE 620–10 1 16 |
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