6.1.3
Power Control ........................................................................................................................... 62
6.1.4
Clock Control ............................................................................................................................ 62
6.1.5
System Control ......................................................................................................................... 64
6.2
Initialization and Configuration ................................................................................................... 65
6.3
Register Map ............................................................................................................................ 65
6.4
Register Descriptions ................................................................................................................ 66
7
Hibernation Module .......................................................................................................... 120
7.1
Block Diagram ........................................................................................................................ 121
7.2
Functional Description ............................................................................................................. 121
7.2.1
Register Access Timing ........................................................................................................... 121
7.2.2
Clock Source .......................................................................................................................... 122
7.2.3
Battery Management ............................................................................................................... 122
7.2.4
Real-Time Clock ...................................................................................................................... 122
7.2.5
Non-Volatile Memory ............................................................................................................... 123
7.2.6
Power Control ......................................................................................................................... 123
7.2.7
Interrupts and Status ............................................................................................................... 123
7.3
Initialization and Configuration ................................................................................................. 124
7.3.1
Initialization ............................................................................................................................. 124
7.3.2
RTC Match Functionality (No Hibernation) ................................................................................ 124
7.3.3
RTC Match/Wake-Up from Hibernation ..................................................................................... 124
7.3.4
External Wake-Up from Hibernation .......................................................................................... 125
7.3.5
RTC/External Wake-Up from Hibernation .................................................................................. 125
7.4
Register Map .......................................................................................................................... 125
7.5
Register Descriptions .............................................................................................................. 126
8
Internal Memory ............................................................................................................... 139
8.1
Block Diagram ........................................................................................................................ 139
8.2
Functional Description ............................................................................................................. 139
8.2.1
SRAM Memory ........................................................................................................................ 139
8.2.2
Flash Memory ......................................................................................................................... 140
8.3
Flash Memory Initialization and Configuration ........................................................................... 141
8.3.1
Flash Programming ................................................................................................................. 141
8.3.2
Nonvolatile Register Programming ........................................................................................... 142
8.4
Register Map .......................................................................................................................... 142
8.5
Flash Register Descriptions (Flash Control Offset) ..................................................................... 143
8.6
Flash Register Descriptions (System Control Offset) .................................................................. 150
9
General-Purpose Input/Outputs (GPIOs) ....................................................................... 163
9.1
Functional Description ............................................................................................................. 163
9.1.1
Data Control ........................................................................................................................... 164
9.1.2
Interrupt Control ...................................................................................................................... 165
9.1.3
Mode Control .......................................................................................................................... 166
9.1.4
Commit Control ....................................................................................................................... 166
9.1.5
Pad Control ............................................................................................................................. 166
9.1.6
Identification ........................................................................................................................... 166
9.2
Initialization and Configuration ................................................................................................. 166
9.3
Register Map .......................................................................................................................... 168
9.4
Register Descriptions .............................................................................................................. 169
November 30, 2007
4
Preliminary
Table of Contents