Figure 13-13. Slave Command Sequence ............................................................................................ 323
Figure 14-1.
CAN Module Block Diagram ........................................................................................... 348
Figure 14-2.
CAN Bit Time ................................................................................................................ 355
Figure 15-1.
Analog Comparator Module Block Diagram ..................................................................... 389
Figure 15-2.
Structure of Comparator Unit .......................................................................................... 390
Figure 15-3.
Comparator Internal Reference Structure ........................................................................ 391
Figure 16-1.
PWM Module Block Diagram .......................................................................................... 401
Figure 16-2.
PWM Count-Down Mode ................................................................................................ 402
Figure 16-3.
PWM Count-Up/Down Mode .......................................................................................... 403
Figure 16-4.
PWM Generation Example In Count-Up/Down Mode ....................................................... 403
Figure 16-5.
PWM Dead-Band Generator ........................................................................................... 404
Figure 17-1.
Pin Connection Diagram ................................................................................................ 436
Figure 20-1.
Load Conditions ............................................................................................................ 453
Figure 20-2.
I2C Timing ..................................................................................................................... 455
Figure 20-3.
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 455
Figure 20-4.
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 456
Figure 20-5.
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 456
Figure 20-6.
JTAG Test Clock Input Timing ......................................................................................... 457
Figure 20-7.
JTAG Test Access Port (TAP) Timing .............................................................................. 458
Figure 20-8.
JTAG TRST Timing ........................................................................................................ 458
Figure 20-9.
External Reset Timing (RST) .......................................................................................... 459
Figure 20-10. Power-On Reset Timing ................................................................................................. 459
Figure 20-11. Brown-Out Reset Timing ................................................................................................ 459
Figure 20-12. Software Reset Timing ................................................................................................... 460
Figure 20-13. Watchdog Reset Timing ................................................................................................. 460
Figure 21-1.
100-Pin LQFP Package .................................................................................................. 461
9
November 29, 2007
Preliminary
LM3S2110 Microcontroller