List of Registers
10
October 8, 2006
Preliminary
List of Registers
System Control ............................................................................................................................... 48
Register 1:
Device Identification 0 (DID0), offset 0x000 .............................................................................. 56
Register 2:
Device Identification 1 (DID1), offset 0x004 .............................................................................. 57
Register 3:
Device Capabilities 0 (DC0), offset 0x008................................................................................. 59
Register 4:
Device Capabilities 1 (DC1), offset 0x010................................................................................. 60
Register 5:
Device Capabilities 2 (DC2), offset 0x014................................................................................. 62
Register 6:
Device Capabilities 3 (DC3), offset 0x018................................................................................. 63
Register 7:
Device Capabilities 4 (DC4), offset 0x01C ................................................................................ 65
Register 8:
Power-On and Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................ 66
Register 9:
LDO Power Control (LDOPCTL), offset 0x034.......................................................................... 67
Register 10:
Software Reset Control 0 (SRCR0), offset 0x040 ..................................................................... 68
Register 11:
Software Reset Control 1 (SRCR1), offset 0x044 ..................................................................... 69
Register 12:
Software Reset Control 2 (SRCR2), offset 0x048 ..................................................................... 70
Register 13:
Raw Interrupt Status (RIS), offset 0x050................................................................................... 71
Register 14:
Interrupt Mask Control (IMC), offset 0x054 ............................................................................... 72
Register 15:
Masked Interrupt Status and Clear (MISC), offset 0x058.......................................................... 74
Register 16:
Reset Cause (RESC), offset 0x05C .......................................................................................... 75
Register 17:
Run-Mode Clock Configuration (RCC), offset 0x060................................................................. 76
Register 18:
XTAL to PLL Translation (PLLCFG), offset 0x064 .................................................................... 80
Register 19:
Run-Mode Clock Gating Control 0 (RCGC0), offset 0x100 ....................................................... 81
Register 20:
Sleep-Mode Clock Gating Control 0 (SCGC0), offset 0x110..................................................... 81
Register 21:
Deep-Sleep-Mode Clock Gating Control 0 (DCGC0), offset 0x120........................................... 81
Register 22:
Run-Mode Clock Gating Control 1 (RCGC1), offset 0x104 ....................................................... 83
Register 23:
Sleep-Mode Clock Gating Control 1 (SCGC1), offset 0x114..................................................... 83
Register 24:
Deep-Sleep-Mode Clock Gating Control 1 (DCGC1), offset 0x124........................................... 83
Register 25:
Run-Mode Clock Gating Control 2 (RCGC2), offset 0x108 ....................................................... 85
Register 26:
Sleep-Mode Clock Gating Control 2 (SCGC2), offset 0x118..................................................... 85
Register 27:
Deep-Sleep-Mode Clock Gating Control 2 (DCGC2), offset 0x128........................................... 85
Register 28:
Deep-Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .............................................. 86
Register 29:
Clock Verification Clear (CLKVCLR), offset 0x150.................................................................... 87
Register 30:
Allow Unregulated LDO to Reset the Part (LDOARST), offset 0x160 ....................................... 88
Internal Memory .............................................................................................................................. 89
Register 1:
Flash Memory Protection Read Enable (FMPRE), offset 0x130 ............................................... 94
Register 2:
Flash Memory Protection Program Enable (FMPPE), offset 0x134 .......................................... 94
Register 3:
USec Reload (USECRL), offset 0x140...................................................................................... 95
Register 4:
Flash Memory Address (FMA), offset 0x000 ............................................................................. 96
Register 5:
Flash Memory Data (FMD), offset 0x004 .................................................................................. 97
Register 6:
Flash Memory Control (FMC), offset 0x008 ..............................................................................98
Register 7:
Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ................................................. 100
Register 8:
Flash Controller Interrupt Mask (FCIM), offset 0x010 ............................................................. 101
Register 9:
Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014......................... 102
General-Purpose Input/Outputs (GPIOs) .................................................................................... 103
Register 1:
GPIO Data (GPIODATA), offset 0x000 ................................................................................... 111
Register 2:
GPIO Direction (GPIODIR), offset 0x400 ................................................................................112
Register 3:
GPIO Interrupt Sense (GPIOIS), offset 0x404......................................................................... 113
Register 4:
GPIO Interrupt Both Edges (GPIOIBE), offset 0x408.............................................................. 114
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