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T84C5112-RKFIL Datasheet(PDF) 9 Page - ATMEL Corporation |
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T84C5112-RKFIL Datasheet(HTML) 9 Page - ATMEL Corporation |
9 / 97 page Rev. B - November 10, 2000 9 Preliminary T80C5112 6.3. Functional Block diagram Figure 1. Functional block diagram 6.4. Operating modes 6.4.1. Reset : · An hardware RESET select Xtal_Osc or RC_Osc depending on the RST_OSC configuration bit 6.4.2. Functional modes : 6.4.2.1. NORMAL MODES : · CPU and Peripherals clock depend on the software selection using CKCON0, CKCON1, CKSEL and CKRL registers · CKS bit selects either Xtal_Osc or RC_Osc · CKRL register determines the frequency of the selected clock, unless X2 bit is set. In this case the prescaler/divider is not used, so CPU core needs only 6-clock period per machine cycle. According to the value of the peripheral X2 individual bit, each peripherals need 6 or 12 clock period per instructions. · It is always possible to switch dynamicaly by software from Xtal_Osc to RC_Osc, and vice versa by changing CKS bit, a synchronization cell allowing to avoid any spike during transition. Xtal2 Xtal1 PwdRC WD clock PwdOsc Ckrl Reload 8-bit Prescaler-Divider ResetB 1 0 OscOut Xtal_Osc RC_Osc XT_SP OSCBEN OSCAEN CKS X2 0 1 1 0 RCLF_Osc RCLF_OFF Mux Filter + RCLF_OFF OSCA OSCB OSCC CkIdle Ck Idle Cpu clock Peripherals clock Pwd CkOut CkAdc Quiet OSCBEN OSCAEN 0 1 :128 A/D clock Sub Clock Timer 0 clock |
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