C161U

SAF C161U-LF

Interrupt Subnode Control

Addendum

3/6

2002-07-31

3

Interrupt Subnode Control

Page 130.

The ISNC register is defined as follows:

Note: See Data Sheet, Chapter 3.3 for Clock Generation Concept.

EXI6SS

0 0

Must be set to ’00’.

0 1

Not allowed.

1 0

Not allowed.

1 1

Not allowed.

EXI7SS

0 0

0 1

Input from source RTC_INT.

1 0

Not allowed.

1 1

Not allowed.

ESFR-b

15

14

13

12

11

10

987

6543210

PLL

IE

PLL

IR

RTC

T14

IE

RTC

T14

IR

Bit

Function

T14IR

T14 Overflow Interrupt Request Flag

‘0’

No request pending

‘1’

This source has raised an interrupt request

T14IE

T14 Overflow Interrupt Enable Control Bit

‘0’

Interrupt request is disabled

‘1’

Interrupt request is enabled

PLLIR

‘0’

No request pending

‘1’

This source has raised an interrupt request

PLLIE

PLL Interrupt Enable Control Bit

‘0’

Interrupt request is disabled

‘1’

Interrupt request is enabled

Bit

Function