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AT91RM9200-QU-002 Datasheet(PDF) 7 Page - ATMEL Corporation |
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AT91RM9200-QU-002 Datasheet(HTML) 7 Page - ATMEL Corporation |
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7 / 683 page  7 1768E–ATARM–30-Sep-05 AT91RM9200 – Two different Read Protocols for each Memory Bank • Multiple device adaptability – Compliant with LCD Module – Programmable Setup Time Read/Write – Programmable Hold Time Read/Write • Multiple Wait State Management – Programmable Wait State Generation – External Wait Request – Programmable Data Float Time 3.9 SDRAM Controller • Numerous configurations supported – 2K, 4K, 8K Row Address Memory Parts – SDRAM with two or four Internal Banks – SDRAM with 16- or 32-bit Data Path • Programming facilities – Word, half-word, byte access – Automatic page break when Memory Boundary has been reached – Multibank Ping-pong Access – Timing parameters specified by software – Automatic refresh operation, refresh rate is programmable • Energy-saving capabilities – Self-refresh and Low-power Modes supported • Error detection – Refresh Error Interrupt • SDRAM Power-up Initialization by software • Latency is set to two clocks (CAS Latency of 1, 3 Not Supported) • Auto Precharge Command not used 3.10 Burst Flash Controller • Multiple Access Modes supported – Asynchronous or Burst Mode Byte, Half-word or Word Read Accesses – Asynchronous Mode Half-word Write Accesses • Adaptability to different device speed grades – Programmable Burst Flash Clock Rate – Programmable Data Access Time – Programmable Latency after Output Enable • Adaptability to different device access protocols and bus interfaces – Two Burst Read Protocols: Clock Control Address Advance or Signal Controlled Address Advance – Multiplexed or separate address and data buses |
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