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AT91RM9200_0509 Datasheet(PDF) 6 Page - ATMEL Corporation |
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AT91RM9200_0509 Datasheet(HTML) 6 Page - ATMEL Corporation |
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6 / 38 page  6 1768IS–ATARM–30-Sep-05 AT91RM9200 Summary – Each Master can be assigned a priority between 0 and 7 • Address Decoder provides selection for – Eight external 256-Mbyte memory areas – Four internal 1-Mbyte memory areas – One 256-Mbyte embedded peripheral area • Boot Mode Select Option – Non-volatile Boot Memory can be internal or external – Selection is made by BMS pin sampled at reset • Abort Status Registers – Source, Type and all parameters of the access leading to an abort are saved • Misalignment Detector – Alignment checking of all data accesses – Abort generation in case of misalignment • Remap command – Provides remapping of an internal SRAM in place of the boot NVM 3.7 External Bus Interface • Integrates three External Memory Controllers: – Static Memory Controller – SDRAM Controller – Burst Flash Controller • Additional logic for NAND Flash/SmartMedia and CompactFlash support • Optimized External Bus: – 16- or 32-bit Data Bus – Up to 26-bit Address Bus, up to 64-Mbytes addressable – Up to 8 Chip Selects, each reserved to one of the eight Memory Areas – Optimized pin multiplexing to reduce latencies on External Memories • Configurable Chip Select Assignment: – Burst Flash Controller or Static Memory Controller on NCS0 – SDRAM Controller or Static Memory Controller on NCS1 – Static Memory Controller on NCS3, Optional NAND Flash/SmartMedia Support – Static Memory Controller on NCS4 - NCS6, Optional CompactFlash Support – Static Memory Controller on NCS7 3.8 Static Memory Controller • External memory mapping, 512-Mbyte address space • Up to 8 Chip Select Lines • 8- or 16-bit Data Bus • Remap of Boot Memory • Multiple Access Modes supported – Byte Write or Byte Select Lines |
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