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AT91C140 Datasheet(PDF) 11 Page - ATMEL Corporation |
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AT91C140 Datasheet(HTML) 11 Page - ATMEL Corporation |
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11 / 174 page  11 6069C–ATARM–15-Sep-05 AT91C140 8. System Controller The AT91C140 features a System Controller that takes care of and controls: • the Test Mode • the Reset • the System Clocks • the Chip Identifier The System Controller manages the reset of all the system and integrates a clock generator, made up of an oscillator and a PLL. 8.1 Test The AT91C140 features a test pin (TST). This pin must be tied low for normal operations. Using the AT91C140 with the TST pin at a high level might lead to unpredictable results. 8.2 Reset Controller 8.2.1 NRST Pin The AT91C140 is reset by asserting the NRST pin low. It should be asserted for a time ade- quate to ensure the startup of the oscillator on a power on, and at least 1 ACLK cycle for a warm reset. As the ACLK switches on the 31,25kHz (assuming the crystal is at 16 MHz) as soon as the reset is asserted, it must remain low for at least 32 µs. The first instruction fetch happens 10 ACLK cycles after the reset releases. 8.2.2 System Reset A reset initializes the user interface registers to their default states as defined in the peripheral sections of this datasheet and forces the ARM7TDMI to perform the next instruction fetch from address zero. Except for the program counter and the Current Program Status Register, the ARM processor registers do not have defined reset states. When NRST is active, the inputs of the AT91C140 must be held at valid logic levels to reduce the power consumption to a minimum. 8.2.3 Boot Memory and Remap Command When NRST is released, the PA0 pin is sampled to determine if the ARM processor should boot from internal ROM or from external memory connected to NCE0. The details of the boot operations are described in ”Memory Controller (MC)” on page 16. The Boot Program is described in ”Boot Program” on page 24. After a reset, the RM bit in the Mode Register reflects the state of the PA0 pin. Then, writing this bit at 1 removes the ROM from the address 0. Writing it at 0 remaps the ROM at address 0x0. 8.3 Clock Generator The AT91C140 features a Clock Generator based on a 16 MHz oscillator and a PLL. It pro- vides all the clocks of the system, including a clock signal named ACLK, to the ARM processor, to the memory controller and to the External Bus Interface and to all the embedded peripherals The ACLK signal is also provided on the ACLKO pin, through PIO Controller A. Figure 8-1 below shows the architecture of the Clock Generator. |
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